Drill Down: Embedded NVM Technology

Many of the next-generation devices that will be seen on the IoT/E will have power, footprint, and electronic constraints as never before. Electronic flash memories (eFLASH), and their derivatives are seen as a realistic solution to many of these design constraints for small form factor and simple IoE devices.

“NVM will be very important for the IoE from the perspective of saving power,” says Steve Woo, vice president of enterprise solutions technology at Rambus. “It doesn’t consume any power during non-use, which is a requirement for many of the low-power IoE devices that are going to need to draw very little power during turn on and turn off, and no power at rest.”

Semiconductor Engineering addressed some of these technologies in a previous story. This article will take a deeper look at some of these platforms.

The technologies discussed here are all derivatives of ReRAM (also called RRAM) and originally based on the programmable metallization cell (PMC), developed by Arizona State University. They all have similar characteristics, but each technology is different enough to warrant individual development tracks, and discussions within this article.

Ferroelectric Random-Access Memory
FRAM (also called FeRAM or F-RAM) is a promising hybrid memory architecture. It is making a resurgence, now that a new paradigm of internetworking is on the horizon — the IoE.

FRAM got its start back in the 1990s, but until recently density issues kept it pigeonholed to mostly special applications. Now that it can be implemented in CMOS, much of what held it back has been eliminated. Look for it to start showing up in more and more places, especially in MCUs, and soon in IoE devices.

Fig. 1: FRAM cell. Courtesy of Fujitsu.

FRAM is a great compromise between straight flash and SRAM. It has several advantages over flash including: low power requirements faster writes, and much improved rewrite erase cycles (better than 10^16 cycles for 3.3 V devices).

It is known for being able to write fast at low power. Typically, flash needs a booster circuit to build up current. FRAM does not. That means it can complete the operation in less than 150ns, using much less power than flash, where flash would require at least 1ms to accomplish the same operation. The reason is that FRAM uses ferromagnetic material in the transistor’s capacitive configuration (see Figure 1). It can overwrite the contents in a single cycle, and the FRAM core is at the CMOS voltage level. Therefore, it does not require that booster circuit (charge pump).

This is a result of using ferromagnetic film rather than a capacitor so when and e-field is applied, it polarizes the lead-zirconate-titanate (PZT) compound. Unlike conventional transistors, the polarization remains once the e-field is removed. Typically, the compound is designed to move along the particular hysteresis loop of the PZT material to one of two stable states; “0” or “1.” This, of course, determines the binary state of the cell. This PZT design allows FRAM to write very quickly, and use very little power in the operation. It also has a couple of other advantages over flash and EEPROM, one of which is much higher read/write cycles.

One of FRAM’s attributes is its use in fast transaction scenarios such as transit card reading. Because it has the capability to respond in ns, it can pass through a transit turnstile, for example, and read and authenticate data, and update any fare changes back to the card – all in less than the blink of an eye. That keeps traffic moving as quickly as possible.

There is a slight downside, however. FRAM still has much lower density than comparable technologies. That becomes a problem when a sizeable memory allocation is needed in a device that is tightly footprint constrained (certain remote sensors, for example). And it still needs 3.3 volts to operate. That makes it unsuitable for very low power, long-life portable applications. However, it is a very good choice for devices where fast memory is required and power conservation is not a prime consideration, such as instrumentation, metering, industrial microcontrollers, automotive, business machines, RFID tags and medical equipment, to mention a few.

Resistive Random-Access Memory
ReRAM is a strong IoE contender because of a number of intrinsic benefits. “There are some things about this platform that make it a bit easier to integrate in terms of the existing SoC design flow,” says Woo.

While still a bit early on the memory development map for geometries lower than 20nm, which is a top-shelf target density, advantages are evident. One major advantage is that is has a simple structure with good scalability. Another is that it offers high speed, with switching times as low as 10ns, at low power. It has the ability to switch a bit using only 1 femtojoule. And it has a very desirable feature—ease of integration with CMOS back-end-of-the-line processes. Finally, it has the potential to be built in extremely dense crossbar arrays. “But there are still a number of technical issues to work out, at least from the integration with existing manufacturing processes, adds Woo.

ReRAM uses resistance rather than electrical charges to change the bits within the cell. The principle is that when voltage is applied, the resistance changes. The state change is, of course, from zero to one, or vice versa. Being a type of NVM, once the state is set, it remains set until the next change cycle.

However, not all ReRAM is alike. One type of composition is shown in Figure 2. Depending on what the application may be, the different types can have different underlying material, which support distinct properties, such as various access times, retention capability, and power consumption. For example, certain fabrications provide best-of-breed data retention while others can exhibit extremely fast read/write times. “In the future, when one is talking about IoE devices, by far the No. 1 design goal is to have as small as possible power budgets,” says Woo. It seems that ReRAM might just fit that bill.

ReRAM makes use of a “memristor,” or memory resistor. This is a form of passive circuit element, which maintains a relationship between the time integrals of current and voltage across a two-terminal element. Essentially, it is a nanoscale voltage-controlled resistor.

Fig. 2: ReRAM cell, courtesy of PhoneArena.com.

One type of ReRAM consists of titanium oxide as an insulator. One side of it contains oxygen molecules, which move across to the other side if a voltage potential is placed across it, reflecting a “1” state. Returning the oxygen molecules to the other side returns the memory to the off state.

Typical applications for ReRAM include computer memory, microcontrollers, smart phones, tablets, automobile navigation systems, and digital cameras, for example. Once high-density arrays can be reliably produced, ReRAM will have a lot of applicability for IoE devices that need fast switching and low power. And, its flexible configurability, via materials, means it can be used in a wide variety of IoE devices.

Phase-Change Memory
PCM (or CBRAM, C-RAM and a couple of other acronyms) is in the same family as ReRAM but its resistive properties are owed to what is called chalcogenide glass, which has some rather unique electrical behavioral properties. It works on the principle of a reversible, electrochemically induced conduction channel that uses a special dielectric as an ionic conductor (see Figure 3).

Fig. 3: PCM schematic, courtesy of Micron.

In other words, it relies on the state of the glass for its electrical properties. The material structure has the ability to rapidly alter back and forth between crystalline (ordered) or amorphous (disordered) conditions on a microscopic scale. In the amorphous state the material has high electrical resistance. In the crystalline state its resistance is reduced. The changes in these states is what facilitates or halts the flow of current, hence we have the digital equivalents of the ones and zeroes.

Like its cousin, ReRAM, PCM can be high-speed (as low as 10ns), low-power (less than 1 volt, with a few A) high-density, and inexpensive. It is a three-dimensional structure, which presents the opportunity to optimize the density/footprint equation. Of particular note is that it can rewrite without erasing the cell, first. That is a critical advantage in both speed and power metrics and makes it an ideal component for things like medical devices, low-end appliances, wearables, and smartphones, for example.

Magnetoresistive Random Access Memory
is another one of the advanced nonvolatile technologies. MRAM also isn’t new. It was first introduced in the early 1990s at various technical conferences. However, only recently have derivatives such as field-switching and heat-assist MRAM, and the most promising, spin-transfer torque (STT) MRAM, emerged as contenders for IoE device memory (see Figure 4).

Fig. 4: MRAM device, courtesy of Ed Grochowski.

This latest MRAM has a number of “new and improved” circuit designs. One is that it divides the current paths for read and write operations. That greatly improves read speed times. That, in turn, reduces the equivalent resistance (Req) of the write operation by nearly 40%. These new advances can offer a cycle time of 34ns, which translates into a read/write speed of 200 megabytes per second. Moreover, this performance is underlined by a low operating voltage of only 1.8V, which makes it useful for modern portable digital products on and off the IoE.
MRAM is another technology that uses standard CMOS processes. Again, it can be handled by the traditional back-end of line, which makes for a seamless manufacturing process enabling high-yield, low-cost devices that can be competitive in the lower end of IoE devices, discrete and embedded.

It also has the advantage of a single-transistor cell, making it a good contender for single-chip integrations. “This is the kind of technology that can easily be integrated into the SoC manufacturing process,” says Woo.

Silicon-Oxide-Nitride-Oxide-Silicon
The last, but certainly not least, entry in this arena is SONOS (see Figure 5). This type of memory uses, silicon nitride, which contains traps that capture the carriers that are injected from the one of the channels of a MOS Transistor. These traps hold that charge. SONOS also boast considerably lower program and erase voltages than typical floating gate devices.

A key parameter of SONOS memory is that it uses Fowler-Nordheim (F-N) tunneling to both set and erase. That makes it unnecessary to use the traditional hot electron injection (HEI) for programming, making the device very robust. That robustness is also enhanced by the fact that the charge is held in an insulating layer, making data retention, inherently, more reliable.

A typical configuration of a SONOS cell includes two transistors. One is the SONOS device; the other, for this discussion, is an NMOS transistor. The cell set and erase scenario goes something like this: First, the gate voltage of the SONOS transistor is raised to a specific positive value. Then the electrons are injected into tunnel oxide, using FN tunneling. The device is erased by applying the required negative voltage to the gate, which causes FN tunneling of holes from the substrate to the charge storage layer. The required program and erase voltage between the gate and substrate is obtained by applying appropriate voltages to the gate and the p-well.

Fig. 5: Schematic of SONOS transistor (a) and voltage characteristics of states, courtesy of Intech.

SONOS doesn’t come in near the front of the pack when it comes to state-change metrics. That isn’t its claim to fame. Where it shines is in applications that are not particularly sensitive to power budgets or fast response time. It also can hold data for up to 10 years, and plays well with standard SoC manufacturing processes.

SONOS has a relatively simple structure. It can use the same poly gate as the logic and by replacing the gate oxide with an ONO compound gives it the ability to easily scale, either the gate-first or gate-last, up to high-K metal gate processes. Because SONOS has low thermal budget it presents a negligible impact on electrical parameters of existing CMOS devices.

Missive
While NVM technologies have been around for quite a while, the requirements of new paradigms, such as the IoE, and everything connected to everything else, are placing new demands on these technologies. As a result, NVM technologies are undergoing a revolution. Both new and existing technologies are under the microscope for footprint, functionality, technology, and integration.

There are many avenues that are going to evolve over the next few years as much of this brave new world unfolds. There will be no “one size fits all,” but there will be many sizes and many options. Economies of scale will play a role, as will Moore’s law.

“The end point for IoE-type devices is that one really wants to try and have on-chip non-volatile memory,” says Woo. “When you are moving data, you really want to move it the shortest distance possible.” That is the driving force. And embedded NVM memory on the same chip as the MCU or other controller silicon will, for now, make the best IoE devices, at least for now.