Driving Toward More Rugged, Less Expensive SiC

Silicon carbide is gaining traction in the power semiconductor market, particularly in electrified vehicles, but it’s still too expensive for many applications.

The reasons are well understood, but until recently SiC was largely a niche technology that didn’t warrant the investment. Now, as demand grows for chips that can work in high-voltage applications, SiC is getting a much closer look. And unlike other potential alternatives to silicon power devices, SiC has the advantage of familiarity.

First used for detector diodes in crystal radios, SiC was one of the first commercially important semiconductors. Commercial SiC JFETs have been available since 2008, and are especially useful in electronics for extreme environments. SiC MOSFETs were commercialized in 2011. The material offers a moderate bandgap of 3.26 eV, with 10 times the breakdown voltage of silicon.

Unfortunately, SiC is also very difficult to manufacture. Tobias Keller, vice president of global product management at Hitachi Energy, explained that standard Czochralski (CZ) growth methods are not viable. CZ growth melts silicon in a silica crucible at about 1500°C, but silicon carbide’s melting point is above 2700°C.

Instead, SiC crystals are usually grown by the Lely method. SiC powder is heated to more than 2500°C in an argon atmosphere, where it sublimes onto a seed crystal. The process gives adequate results, but it is defect-prone and difficult to control. Engineers performing inspection of incoming SiC wafers typically identify substantial “dead” areas due to stacking faults and other defects.

SiC devices are built on a custom epitaxial device layer optimized for the anticipated operating voltage. Thicker epilayers can tolerate higher voltages, but they also tend to have more defects. Over the last two years, improved wafer quality and earlier identification of dead areas have boosted overall yield by 30%, Keller said.

Better dielectrics for higher mobility
SiC MOSFETs are further limited by the generally poor quality of the gate oxide/carbide interface. In work presented at December’s IEEE Electron Device Meeting (IEDM), researcher T. Kimoto and colleagues at Japan’s Kyoto and Osaka Universities explained that carbon-carbon defects at the interface appear to result from direct oxidation of SiC. [1] These defects lie near the SiC conduction band edge, where they increase channel resistance and contribute to threshold voltage shifts in the finished devices.

As an alternative to oxidation of SiC, Kimoto’s group first etched the surface with hydrogen plasma, then deposited SiO₂ by CVD, followed by nitridation of the interface. This process reduced trap density and more than doubled inversion layer electron mobility to 80 cm²/V-sec at 10V gate bias.

Stephan Wirths and colleagues at Hitachi Energy (formerly ABB Semiconductors) demonstrated that an unnamed high-k dielectric compound could form low-defect interfaces with SiC, without the passivation steps needed for SiO₂. [2] As in silicon devices, using high-k gate dielectrics for SiC MOSFETs also increases the physical thickness at a given capacitance, reducing gate leakage current.

Fig. 1: High-k SiC power MOSFET. Source: Hitachi Energy

The poor mobility of SiC carriers poses another challenge for device designers. Even after decades of work, the best mobility achieved by optimizing the gate dielectric is still less than silicon’s by a factor of 10. As a result, channel resistance is correspondingly 10 times higher than silicon’s.

In power devices, low mobility limits both performance and durability. Device resistance and switching losses directly impact such parameters as the range of an electric vehicle. While implanted dopants and structural modifications can reduce the channel resistance, James Cooper, president of Sonrisa Research, observed that doing so also reduces short circuit withstand time by increasing current density. [3]

Surviving short circuits
The short circuit withstand time is an important safety parameter for power devices. If the device is short-circuited for any reason, it needs to survive long enough for protective circuits to respond. Failure risks not only permanent damage to the electric load, but also user injury, fires, and property damage. The exact requirement depends on the design of the protection circuit, but it typically is from 5 to 10 microseconds. As current density increases, so does the temperature under short circuit conditions, and the withstand time decreases.

Commercial adoption of SiC MOSFETs has been slow in part because these devices tend to have shorter withstand times than similarly rated silicon devices. For this reason, designers would like to change the relationship between channel resistance and current density. Is it possible to reduce the resistance without increasing current density to dangerous levels?

One possible solution is to reduce the gate bias while also reducing the oxide thickness. Cooper explained that a thinner oxide improves control of the channel — as in silicon MOSFETs — allowing lower voltage operation. This solution requires very little change to the manufacturing process. While few studies of SiC devices with thin dielectrics exist, silicon devices use oxides as thin as 5nm without undue tunneling. Moreover, as noted above, the use of high-k dielectrics can give better channel control while maintaining physical thickness.

A second alternative, proposed by Dongyoung Kim and Woongje Sung at SUNY Polytechnic Institute, seeks to reduce current density by increasing the effective channel thickness. They used a 4° tilt angle to implant deep P-wells, exploiting ion channeling along the <0001> SiC lattice direction. This approach requires only minor changes to the manufacturing process, as the deep well implant uses the same mask as a conventional well. The resulting devices reduced maximum drain current by about 2.7 times and increased withstand time by a factor of four. [4]

To solve a similar problem, the silicon industry turned to the now ubiquitous finFET. Increasing the channel area at constant current reduces the current density. Researchers at Purdue University demonstrated a SiC tri-gate MOSFET with polysilicon gates and multiple sub-micron fins, achieving a 3.6X reduction in specific channel resistance. [5]

Fig. 2: Current paths and channel width in a tri-gate SiC MOSFET. Source: IEEE Electron Device Letters

While it’s not clear how quickly the power device industry would adopt an architecture as radical as the finFET, the high breakdown voltage of SiC is a compelling advantage. Manufacturers hoping to realize that advantage will need to find a solution to the challenges posed by low mobility and high current density.

References
[1] T. Kimoto et al., “Physics and Innovative Technologies in SiC Power Devices,” 2021 IEEE International Electron Devices Meeting (IEDM), 2021, pp. 36.1.1-36.1.4, doi: 10.1109/IEDM19574.2021.9720696.

[2] S. Wirths et al., “Vertical 1.2kV SiC Power MOSFETs with High-k/Metal Gate Stack,” 2019 31st International Symposium on Power Semiconductor Devices and ICs (ISPSD), 2019, pp. 103-106, doi: 10.1109/ISPSD.2019.8757601.

[3] J. A. Cooper et al., “Demonstration of Constant-Gate-Charge Scaling to Increase the Robustness of Silicon Carbide Power MOSFETs,” in IEEE Transactions on Electron Devices, vol. 68, no. 9, pp. 4577-4581, Sept. 2021, doi: 10.1109/TED.2021.3099455.

[4] D. Kim and W. Sung, “Improved Short-Circuit Ruggedness for 1.2kV 4H-SiC MOSFET Using a Deep P-Well Implemented by Channeling Implantation,” in IEEE Electron Device Letters, vol. 42, no. 12, pp. 1822-1825, Dec. 2021, doi: 10.1109/LED.2021.3123289.

[5] R. P. Ramamurthy, N. Islam, M. Sampath, D. T. Morisette and J. A. Cooper, “The Tri-Gate MOSFET: A New Vertical Power Transistor in 4H-SiC,” in IEEE Electron Device Letters, vol. 42, no. 1, pp. 90-93, Jan. 2021, doi: 10.1109/LED.2020.3040239.