Executive Outlook: Chiplets, 3D-ICs, and AI

Semiconductor Engineering sat down to discuss chiplets and the challenges of moving to 3D-ICs with Bill Mullen, Ansys fellow; John Ferguson, senior director of product management at Siemens EDA; Chris Mueth, senior director of new markets and strategic initiatives at Keysight; Albert Zeng, senior engineering group director at Cadence; Anand Thiruvengadam, senior director and head of AI product management at Synopsys. What follows are excerpts of that discussion, which was held in front of a live audience at ESD Alliance 2025.

L-R: Ansys’ Mullen; Siemens’ Ferguson; Keysight’s Mueth; Cadence’s Zeng; Synopsys’ Thiruvengadam.

SE: Leading-edge chipmakers are running out of options for scaling in two dimensions. We’re starting to see multi-die assemblies and chiplets inside of hyperscale data centers, and that will continue. The challenge now is how to bring the rest of the semiconductor ecosystem along with this. So how do we get there?

Mueth: Standards become very important here. There’s a methodology for designing an integrated circuit, and over the last few decades we’ve gotten very efficient as an industry. We have IP providers and standards to make it easy to deal with hierarchy. We have multiple companies, so you don’t have to develop everything yourself. And there is this concept of a chiplet economy, where instead of Arm providing a core that goes onto an SoC, some vendors would provide chiplets that others would integrate into 3D-IC systems. There’s a lot of opportunity there, but there’s a lot of new challenges, and we’ll see how that evolves as the standards and the cooperation among companies play out.

Ferguson: We’re already there in cases where performance and integration are the drivers. But those have to be traded off against cost, because chiplets aren’t cheap. In cases where you have high data rates or high bandwidth, or these incredibly integrated assemblies, chiplets make sense. It’s happening today. But we need more use cases like that. But how do you enable it in general? Right now, the industry is stuck on how to incorporate the processes and packaging technology to enable that, and how to test those chiplets, which are incredibly complex and really difficult to test because you can’t probe everywhere inside a chiplet. So we need to come up with new methodologies for that. Standards are good, because an individual company doesn’t have to reinvent the wheel. Chiplets typically would be custom products anyway. But if you’re guided by standards — and the test industry, for example, is adhering to a standard — then you don’t have to reinvent the wheel yourself. You’re sharing the expense and the burden of tooling up for these kinds of technologies.

SE: We’ve been talking about chiplets for a very long time. They still don’t go together very easily, even from companies that are developing their own, right?

Ferguson: Absolutely, and that’s a big part of the problem. How do you take these disaggregated chips and put them all together in a way that you know is going to work reliably, with reasonable yield, and still meet your targets. It’s not nearly as easy as the old two-dimensional design process that we’ve known for a long time and we’ve gotten used to. You do a lot of the same steps, but many, many more of them because you have all these different chips and processes you’re putting together. You also have the additional expense that comes along with it. It’s not as easy as having a PDK and the process technologies that go along with it. You have to pull these from different places because it’s not always the same vendor. You’re taking on a big risk here. People are not going to jump into it right away. You’ve got to wait until you’ve got a technology that’s right for it — one that’s going to make enough money to justify the risks and the costs.

Thiruvengadam: That’s pretty much what is driving the need for AI across different parts of the ecosystem. For example, if you’re talking about chiplet integration, there are a lot of complexities that have a significant impact on productivity. And what we’re seeing is, essentially, a widening gap between traditional scaling versus what you need from the industry in terms of the ability to monetize and address that gap. That translates into a huge impact on productivity and the market, and that’s where AI comes in. A lot of our customers are facing a productivity challenge, and they are requiring AI-driven solutions to address the productivity gap.

Zeng: On the ecosystem side, we need standards for stacking. A big challenge is how you’re going to make sure all the bumps are aligned and all the signals are aligned. TSMC has a standard with 3Dblox to minimize entropy. That’s a good direction. When designing a chiplet, you sign-off by yourself. But when you put them together, you need to provide some model for people to simulate at a 3D-IC level. You need to be able to describe the power,  thermal effects, warpage, and stress of your chip. That’s a requirement for people to put them together. If you just provide GDS, how are you going to ask people to put such a big system together and do the analysis?

Mullen: To build on that, you can’t just hand over the GDS because it’s often coming from multiple vendors. The HBM vendor needs to hand off a model of the memory die to the GPU vendor, but they need to make sure those dies work together. So it’s IP protection that becomes very important. We have to have multi-physics models that are efficient, that work together, and that protect the IP of the different companies involved in the ecosystem.

Mueth: This requires concurrent engineering. If you’re designing the product for performance, then you need to bring in the manufacturing and material science part of it and move that up front in the design process so you can make the tradeoffs on thermal and mechanical stress, and on how you assemble things. This is screaming for a platform where you can bring that all together.

SE: While standards would certainly be helpful, almost all the designs that have been done with chiplets, and even some of the advanced packaging, have been one-offs. How do standards fit in here?

Ferguson: That’s part of the challenge. The biggest standard in this industry is a spreadsheet. Everybody has to create their own at some level. What we try to do is pull together some platforms that will help you, and to capture that information and aggregate it as best as possible. But there’s still always going to be some human engineering involved.

Mueth: Some of the commonality would be the processes themselves. So the application, or the family of applications that you’re addressing may vary, but it’s still largely custom. But if you come up with a recipe for doing the packaging, and deploying the packaging, that part of it is likely leveragable from application to application.

SE: Several leading-edge foundries have floated that idea of a limited number of pre-tested options for advanced packaging because they know those components will work together. Is that going to work?

Mullen: There needs to be more than that, and there are efforts in this direction. There’s UCIe and Bunch of Wires. There are a number of protocol standards being developed, as well. I believe they’re trying to come up with common bump pitches or hybrid bond pitches. It’s in the early phases, but that will gain momentum as people push toward multi-vendor chiplet integration.

Ferguson: Some foundries are going even further than that. They say, ‘Tell us what you’re trying to hook up and we will put together where they should be placed and how that should be done.’ It takes time for the foundries to make those decisions. The nice thing is that if they mess it up, it’s not on you. But it does waste time, and it raises questions about how they make those decisions. Is there something the design team could have done to get a little more margin out of it? You don’t get to see how the sausage was made.

SE: How does this compare with standard IP?

Zeng: For IP, there are standard ways to describe it. It’s been in the EDA ecosystem for quite some time, and people already use it to do multiple tape-outs. With chiplets, one of the challenges is that you now need to consider multi-physics effects. That’s very different than the traditional IP approach in a monolithic design. You have to consider the impact of temperature gradients on your design. What’s the impact of voltage-induced warpage? We really need a standard for modeling. A lot of vendors already have the tools to generate models for their own designs. What we don’t have are interchangeable models that can be used by all the tools and then validated.

Thiruvengadam: That’s a fair point. Another aspect is the design integration capabilities. We need a solution that can be a single platform to harness together different abstractions. This is another important technology requirement, irrespective of which customer or vendor it is. You also need to have that higher-level view where you can actually bring together different companies’ chiplets. Think of it as an over-arching platform.

SE: As we get into this chiplet world, we’re also starting to see more serious discussion about 3D-ICs. We’ve been hearing about this for probably a decade at the leading edge. The OSATs, the foundries, and the EDA tool vendors are all looking at this as the next big breakthrough in power and performance, and the only way to achieve orders of magnitude improvements in power and performance. But now you have to deal with issues around thermal dissipation, verification, and the overall design flow. Let’s start with heat. How do we cool these devices?

Mullen: There’s no single solution. There’s a huge industry looking at things like microfluidics, liquid cooling, two-phase cooling, and immersion cooling. Those are all under investigation. Diamond materials are being investigated. You need to get a massive amount of heat out of these systems, which may have power density of thousands of watts in a very small area. So there are going to be a lot of elements, and data centers are changing as a result of it. Many different aspects will need to be addressed to make this practical.

Ferguson: It also includes new materials like glass, ceramics, other ways to hold the heat or remove it.

Mueth: There’s a manufacturing material science problem, where you need to incorporate thermal interface materials. There’s also the option of throttling the voltage, the clock frequencies, and the operations to help manage the heat. But it all comes down to spreading heat, and that’s not a trivial problem to solve.

Zeng: To solve the heat problem we need to look at it from two aspects. One is from the design side. Traditionally, the chip designers didn’t care about heat. They would just design that chip and send it to the system-level designer, hoping they can solve it either from the package point of view or with a heat sink. I went to a factory where they were assembling an H400 system and looked at the heat sink, which was really tall. That’s not going to work in the future. We need to start thinking about thermal at the start of the design of the system. ‘Is this floor plan really heat friendly?’ They need to start running those analyses at the very beginning. Secondly, on the system level, we’re seeing other innovative things to address this problem, including direct cooling, cold plates, and two-phase immersion cooling. I went to a startup company that designed their chip using direct cooling. They put a lot of different cores in there, and based on a map of the heat the chip will generate, they will directly inject liquid into those areas that can generate hotspots. That is a very innovative approach to start bringing the design of the chip, the cooling, and the physical design together.