Extending EUV Beyond 3nm

Jan van Schoot, senior principal architect at ASML, sat down with Semiconductor Engineering to talk about how far EUV can be extended and where it is today. What follows are excerpts of that discussion.

SE: High numerical aperture EUV has been in the works for some time as a way of extending EUV. How is this technology shaping up?

van Schoot: I’m working quite long on high-NA. I already thought about it when we were talking about the NXE:3100 (NA=0.25). I started it with a two-person team. At this moment, we’re now a significant team—100-plus including many top architects. At Zeiss there are even more people involved, because they run the lens and the optics, and therefore need to be significantly ahead of us.

SE: When do you see this actually taking off? We’ve been hearing about it for at least five years.

van Schoot: We’re now close to ramping our design team. Our target is to have the first two machines out in 2020 to 2023.

SE: Is it tied to any particular node? Is it going to be 5nm or 3nm?

van Schoot: I’m struggling with nodes, which for some companies have become marketing terms. We tend to go with the Intel numbers. Using their terms, it could be 3nm.

SE: How far beyond that will it extend?

van Schoot: It will be possible several nodes beyond that, because it cannot be a one-generation tool, of course.

SE: Which means what, using Intel’s node classification?

van Schoot: At least three nodes—3nm plus two subsequent nodes.

SE: What groups will utilize 2nm and 1nm process technology?

van Schoot: The logic guys are most eager to adapt it. We definitely see the DRAM companies being more careful about adopting high NA.

SE: The price of designing a 2nm chip is going to be so high that the economics may be hard to justify for all but a few companies. But ASML’s planning to be there for whoever makes that leap?

van Schoot: Yes, that’s correct.

SE: What sort of challenges are you running into from a technology standpoint?

van Schoot: On the chip side, the challenges are basically to fight the line-edge roughness and the photon shot noise. We have to focus on getting enough power on the wafer. You can fight photon shot noise in two ways. You can apply the brute force method, which is applying more photons. You also can try to improve the contrast of the image that you’re applying to the wafer. That is the more elegant approach.

SE: But elegant only works if it’s cheaper, right?

van Schoot: Yes, and that’s the point. The metric of the tool is how many transistors can you spit out per hour per euro. This tool will have a higher number from this respect than its predecessors. If you look at the tool, one of things we had to do was change the field size. Usually we have this full-sized field, and we had to move to half size to maintain the contrast of the image. There was a shadowing effect. We had to change the magnification of the tool, as it was the only way to keep the mask working. While we do that, you have two choices. Either you change the mask size or you change the size of the image on the wafer.

SE: The industry has resisted going to a larger mask size, right?

van Schoot: Yes, and that is a signal we took extremely seriously. It was the key starting point of the design of this tool. With that in mind, we came up with 8X as being a requirement—maybe 7X or close to that—and you end up with a quarter field on the wafer. That reduced our throughput so significantly that we had to think of other ways. We were considering two different mask sizes, but at some point in time we came up with the anamorphic idea.

SE: Like the old CinemaScope lens?

van Schoot: Yes, that was the starting point of the invention. Contrast is critical, and so is throughput. We had to go down to this half size, and that comes with a price. It has a price for the customer because they now only have half size and they need to start to figure out ways to stitch it, at least in the situation where they have big chips.

Fig. 1: Anamorphic mask writing. Source: ASML

SE: And stitching has been really painful.

van Schoot: That’s not an easy process. On the other hand, the majority of chips are significantly smaller than half-field, so anything in your smart phone will not need full field. That can be done just with half-field printing. But they also have to do things throughput-wise. We are coming up with solutions to keep up the speed. If you stitch, you have to swap masks in between the exposures, so we’re looking at solutions to maintain the speed in that situation, too.

Fig. 2: Imaging verification of half-field for Logic N5 clip Metal-1, 11nm lines, with SMO at 8X. Source: ASML.

SE: ASML is moving into metrology and inspection, as well. Did some of that come out of what you are doing here, where the tools weren’t good enough to be able to see what you are doing?

van Schoot: The idea behind this was that the chip wasn’t perfect because of etch, because of the mask, or maybe because of our tool, anyway, so let’s correct for this in some way. That very quickly turned into, ‘You need to do metrology.’ Although we also investigate imaging, the more critical thing is the overlay, where we measure wafers and feed the data back into our tool. That’s the whole concept and you can do it with any metrology, basically. But if you do it with our tools, then we know what we’ve done with it and the interfacing is taken care of. We’ve built our own loops around it.

SE: So one thing is feeding another as you go forward here?

van Schoot: Yes.

SE: Let’s go back to the original topic. What else did you find?

van Schoot: Throughput and productivity are key. The optics are extremely expensive, so you want to compensate. You don’t want to not use it. When the stages are turning around, the optics are not being used. The EUV photons that are being produced, or potentially being produced, are not being used. Those are precious moments. You want to keep the turnarounds as fast as possible. We put a lot of effort in our stages—especially the mask stage, which because of the anamorphic optics runs at 8X the speed of the wafer stage. At some point it has to turn around.At those moments, we need very significant significant accelerations and decelerations to keep the time loss under control.

Fig. 3: Faster stages enable higher productivity. Source: ASML

SE: You have a lot of mechanical engineering in here, right?

van Schoot: Yes, one of the core competencies of ASML is controlling these stages at these enormous accelerations. At the same time, it’s not only controlling the stage. It also is about keeping the rest of the tool extremely silent. It shouldn’t move at all. There is a precious lens in between that’s manufactured at the picometer level. When we start to shake the tool with our stages, we destroy the image.  What we do is totally decouple the optics from what is happening at the stages.

SE: This is a Zeiss lens?

van Schoot: Yes, Zeiss has been our lens manufacturer and partner for a long time. Next to stages, the lens is our other main challenge. We have mirrors that are polished at the picometer level. They are highly aspheric. That’s a manufacturing challenge in itself.

SE: As companies move down to 5nm there are quantum effects to deal with. So now there are questions about how significant these effects will be and whether it will be better to push into advanced packaging than the most advanced nodes. How do you see the market evolving and how does that affect what you are doing here?

van Schoot: The 2.5D packaging is not what we look at in the High-NA team. That’s for other people in the company. We look at the resolution. The main point is that we give ourselves an edge placement error (EPE) budget. It’s all about the edge. When you look at it more precisely, the overlay of the tool places the edge, but the CD also determines where the edge ends up. If you over- or under-expose the line, it replaces the edges, because the line becomes wider or smaller. The line edge roughness, of course, also defines the placement of the edges. Those components together define the edge placement error. That’s what we take into account. Dose and contrast are the key players. They are dominating the budget. The overlay and the global CD uniformity are becoming less important. At a certain point you can’t effectively improve them. They are dominated by the other effects. You have to start to reduce their contributions, so therefore we push for an NA as high as possible.

SE: How much further can you go with NA? What’s the theoretical limit here?

van Schoot: There is not a theoretical limit. You can get close to 1. The problem is that is not only about angle, it is also about angular spread. If you make a tool that is suitable for two angles, which are extremely high, then you can go to an extremely high resolution. But you can only print one pitch. If you want to print more complex structures, then you need angular spread. That is very critical. At the moment we see ourselves limited, especially in the mask. Within the optics, we’re also pushing limits. But the mask at this moment is the most critical thing to do. On the other hand, if we make another step, it has to be a significant step. We are now at 0.55 NA and the next tool, at 0.6 NA, won’t happen. It is too small a step. Whether we can make a next step is still to be seen.

SE: What would be the next one after 0.55?

van Schoot: If it happens, it has to be at least 0.7/0.75.

SE: This is where we’re starting to run into questions about the limits of Moore’s Law, right?

van Schoot: That is one of the things that you have to take into account, yes. On the other hand, you can still stack a lot, and is basically not about resolution. It’s about transistor density.

SE: There’s also an economic interpretation, depending on who’s arguing for or against it.

van Schoot: Moore’s Law is dictated by our customers, and we follow it. So either we deliver the resolution or we don’t. There are two views. From one point, we are driving it. But when we stop driving it, our customers will find different ways to solve their problems. In that way, we’re following the needs of our customers.

SE: Let’s look at some of the market dynamics. Most of this is aimed at the large foundries and IDMs, but there are new players coming into the market. Where does China fit in?

van Schoot: With High-NA, we expect to hit volume after 2023/2024. Maybe that’s the time for the Chinese.

SE: There are a number of vertical markets that are emerging as very important, as well, but not necessarily with the kinds of volume we saw in mobile phones. How important will servers become for EUV?

van Schoot: The server market is definitely going to be something that’s very important. Everybody talks about the Internet of Things. That calls for a lot of servers.

SE: And where is EUV in terms of commercialization of the technology?

van Schoot: Production equipment for High-NA is being installed now. There are big vacuum vessels that measure the optics. It may be a few tens of picometers off here and there. And then they take out a mirror and it goes to a polishing tool, which takes off whatever it found in those metrology towers. The metrology towers are kind of the heart of what’s happening. This is also the first thing they need to build. It needs, of course, a lot of calibration. These are the first components. One of the rings of the vacuum vessels has a diameter of 5 meters. You can run a train through it. It’s a short tunnel. They are building the facilities. The vessels are there. Then they start to populate those vessels in a clean room.

Fig. 4: Inner workings of EUV, circa 2016. Source: ASML

SE: Do you need a whole new skill set? Do people have to be trained in this all over again?

van Schoot: It’s an evolutionary thing of course. It’s becoming bigger, more precise, but some of the techniques we already used in ArF tools. It’s a building up of things. Making an EUV mirror, from a fundamental point of view, is not that different from an ArF lens. But, of course, if you go into the details, then you have to go down to a much finer level. You have to polish much longer. You need new polishing techniques. Materials are becoming very critical. We have multi-layer coatings. There’s a lot the same, but of course there is a lot different. You have to build on what you know and take one step at a time because it’s the only way you make progress.

Fig. 5: ArF patterning vs. EUV. Source: Imec

SE: We’re finding that teams coming in on 7nm are completely different than the teams that are working at 28nm or 16nm.

van Schoot: This is all about complexity and siloing. I see some similarities. Our tool consists of modules, so we have a lens, we have an illuminator, and we have a wafer stage. We also find there are new areas that need attention. Those new areas are addressed in new teams. What we see is that we add new teams, and by adding new teams, you see that they take their space, so you need to redefine the environment of those teams. There are things that are continuously happening.

SE: What you’re talking about is taking silos and repositioning them as you go, which is a more dynamic way of looking at things. We’re not seeing that kind of movement for silos because every time these folks get the flows and their methodology ironed out, there is resistance to re-doing it. As a result, there is a lag.

van Schoot: Our company has this conservatism built in, so that is accounted for already. There are two things that need to be in place. First, you need to make sure you have the right modules defined, where people can work on. On the other hand, you know that whatever structure you define, there’s always stuff in between the structures. So there’s no such thing as the perfect breakdown of your system into components. That is especially where I see my job as a system engineer, because you are the glue between all those components; to make sure you capture everything before you put the system on the market, and even before you start really designing the tool. The moment you really start making the drawings, you freeze a lot and then it’s difficult to get back. Up to that time, I like to start with a small team and keep it small as long as possible. At a certain moment, when you say, ‘Now I have all the big concepts captured,’ then we can start to expand it to a big team and move very quickly.’

SE: Once you start skipping nodes with different teams—say you build a team for 7nm or 5nm—they can adapt very quickly. But the people sitting back at 14nm/16nm have to be completely retrained because 7nm is so different than what they’re doing, and the move between 14/16nm and 7nm isn’t completely linear.

van Schoot: That is also at ASML one of the critical things. And, learning from the past is the other thing. The 3400 is our most recent tool and we want to learn from that, but it is barely in the field. At this moment, we are designing the High-NA tool. You always learn not from the current generation, but from the previous generation—not one generation in the past, but two generations in the past. That is a kind of continuous conflict that you have for determining when you freeze the development, because you want to learn anything from stuff that is happening today, such as contamination and particles and optics lifetime. There are many things we learn and hope to learn from the latest tools, but at some time you have to freeze your designs to make the next step.

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