First Look: 10nm

As the semiconductor industry begins grappling with mass production at 14/16nm process nodes, work is already underway at 10nm. Tools are qualified, IP is characterized, and the first test chips are being produced. It’s still too early for production, of course—perhaps three years too early—but there is enough information being collected to draw at least some impressions about just how tough this next node will be.

So what are the big challenges at 10nm? There are several. Individually they pose challenges, and together, they pose even bigger ones. But unlike previous nodes, all of them have to be solved together.

Multi-patterning
The proposed insertion of commercially viable EUV lithography at 7nm has dramatically increased the anxiety level over 10nm designs. Much has been written about the travails of EUV development, which originally was expected to begin rolling out at 45nm. It’s a big problem on the manufacturing side, of course, but it’s a big problem on the design side, too. It means multiple photomasks will be required rather than one because the 193nm laser beam is too wide, and designers need to take this into account. It’s possible that some devices won’t print as cleanly as they expect, and the more irregular the shapes the higher that possibility becomes.

Design teams will have a choice of triple patterning, self-aligned double patterning (SADP), or litho-etch-litho-etch-litho-etch (LELELE). While these techniques are well understood, each of them can cause a boatload of problems if any changes are made to original layouts. In fact, if any single factor can be blamed for raising serious questions about the future viability of Moore’s Law, it’s the uncertain progress in lithography.

“Most people have given up on EUV at 10nm,” said Joe Sawicki, vice president and general manager of the Design-To-Silicon Division at Mentor Graphics. “The surprise was that most people didn’t really notice double patterning at 20nm. But triple patterning is a harder problem to solve because people have to do some of this at the IP level. SADP gives you two different qualities of metal. So half the wires will have one set of characteristics and half will have another. That creates more complex routing.”

It also makes timing much more difficult, because a signal will move through some wires faster and with lower power than another. Imagine what happens, for example, when multiple cores are working simultaneously and signals need to be synchronized across wires with different speeds.

Not all layers will require multi-patterning. This roughly follows design at 14/16nm (using a 20nm back-end of line process) where double patterning was required for some metal layers and not others. But those that do also will require more colors—one per mask layer—adding to what is expected to be a steep learning curve.

“The key thing to keep in mind is that you need to be very careful in planning, because there is a lot of complexity,” said Mitch Lowe, vice president of research and development at Cadence. “Part of this involves the via layers with multi-patterning. If you put down power structures they need to be aligned with the patterning. With a clock, that involves routing and shielding. And the cells are very small, particularly at the lower levels. So you’re dealing with more detailed rules between objects that are frequency-dependent and voltage-dependent.”

Electromigration
Electromigration grows worse at 10nm, as well. EM is the displacement of atoms as a result of current flowing through a conductor. Until 20nm, chipmakers relied on a capping layer of silicon carbon nitride and a copper alloy to control EM—basically using a barrier to keep the atoms from moving. New designs will require new materials for capping layers, most likely cobalt compounds. But while these materials have seen some traction at older processes, they will need to be well tested at 10nm before they enter mass production.

“Electromigration is an issue every time we talk about skinnier wires,” said Mary Ann White, director of product marketing for the Galaxy Design Platform at Synopsys. “It’s too early to say how this will affect 10nm designs. Even though tapeouts are happening, it’s largely existing designs going through that process to get an indication of what we’re dealing with. The silicon is still not well characterized.”

10nm process and EDA tools and flows have been under development for several years. Typically, processes move from 0.1 to 0.5 to version 1.0, which is when it is production-ready. The current 10nm processes haven’t even hit version 0.1 yet. That leaves a lot of questions unanswered.

Cadence’s Lowe said some of the biggest unknowns involve clocks, particularly in high-frequency designs. “All of this needs to be planned,” he said. “Some things can’t be solved late. So if you have EM rules or signal EM problems, in the past you would change the device or widen the wire. But on a multi-patterning level, that can cause a big ripple. Anything involving signal processing routing needs to be included in the planning.”

Intellectual property
Rules are key here. Design teams have been working with an increasing number of restrictive design rules for the past three process nodes, and the number of rules will only increase. That also makes it harder to develop commercial IP that can be partially customized, though, and it takes longer to characterize and qualify what is developed.

“The paint is still wet at 16/14nm,” said Mike Gianfagna, vice president of marketing at eSilicon. “We haven’t seen all the issues there. The tools are rolling out at 10nm, and from a semiconductor supplier point of view we still need to understand yield, go through yield learning and improve the process. We’re also seeing process corners on steroids.”

The typical solution at older nodes was to guard band everything, at least initially, and work through the problems afterward. That became far more difficult at 16/14nm, when that extra margin began affecting power and performance. At 10nm, precision in design will be even more important.

“At least these days we’ve gotten smarter about how to look at problems,” said Gianfagna. “We know what to watch for. In the past we got blindsided.”

In fact, some of the learning at 10nm is a progression from 16/14nm, which is why some of the large chipmakers and design houses are developing chips at that node even if they ultimately skip the process node.

“Implementation and manufacturing will become more of a challenge, although the principles used in 16nm remain the same at 10nm,” said Radhakrishnan Pasirajan, vice president of silicon engineering at Open-Silicon. “But colored multi-pattern techniques eventually will be limited. Intel and others have the process capability and their own secret sauce to deal with this. I’m certain that on the day it is widely available for us, the ecosystem will be ready. But the need to go down to those technology nodes is uncertain. There may not be that many people that see a need to migrate.”

Pasirajan said one of the other options is stacking die, using a 10nm engine on one tile or die that is connected to other dies at older nodes. While many industry experts believe this is inevitable, they are surprised by how long it has taken for this packaging approach to begin ramping up.

Other issues
On the system-design side, things get more complicated in other ways, too. Questions are beginning to be asked regularly about soft errors in more densely packed chips using smaller features. Memory makers have been dealing with this for some time, but logic designers have not.

“We don’t know if it’s a problem yet,” said Kurt Shuler, vice president of marketing at Arteris. “But we are getting asked whether you need to protect traffic with ECC or parity bits. You might expect this in automotive and industrial, but not at the lower nodes. But with the profile of wires changing you need to consider this—they’re being made taller than wide to deal with RC effects.”

This helps explain why many of the interactions between the design side and the process side are highly structured. “We do care about wiring planning, because without it you see ever-increasing design margins,” said Drew Wingard, CTO at Sonics. “That has a big impact on our customers and what applications deal with back-end design complexity and cost. We’re not on the verge of collapse of ASIC design, but it is getting harder.”