Improving GaN Device Architectures

As the universe of applications for power devices grows, designers are finding that no single semiconductor can cover the full range of voltage and current requirements. Instead, combination circuits use different materials for different parts of the overall operating range.

GaN is especially well-established in low-power applications like chargers for personal electronics, while silicon and SiC have the advantage in high-power applications. The recent IEEE Electron Device Meeting featured numerous variations on this theme. For example, Florin Udrea, co-founder and CTO at Cambridge GaN Devices, combined an “integrated circuit enhancement GaN” (ICeGaN) module with a silicon insulated gate bipolar transistor (IGBT) to build a traction inverter for electric vehicles. The ICeGaN module includes GaN high electron mobility transistors (HEMTs), along with sensor and surge protection components.[⁠1]

GaN HEMTs meet silicon, silicon carbide transistors
In GaN HEMTs, charge transport primarily depends on a two-dimensional “electron gas” (2DEG). The 2DEG forms because tensile strain at the interface between AlGaN and GaN leads to spontaneous polarization and a discontinuity in the band structure at the interface. Electron mobility is high — on the order of 1500 cm²/volt-sec — inside the polarized region, but low outside of it, which effectively confines carriers near the interface.

In HEMTs, the 2DEG region lies between two plates of a capacitor. In depletion-mode devices, when the top plate — the gate — is positive, it induces a positive charge on the opposite plate. Negative carriers (electrons) are depleted from the channel and accumulate at the two plates, which reduces conductivity. Depletion-mode devices are normally “on.” Current flows when the gate voltage is less than the threshold voltage. But normally “on” devices are undesirable in power control applications for safety reasons.

In contrast, enhancement-mode devices, like the ones used in Udrea’s ICeGaN module, are normally “off.” When the gate voltage is less than the threshold voltage, no current flows. When the device is switched on, a positive charge on the gate pulls electrons from p-doped bulk material into the channel. The ICeGaN module is more efficient when the drain-source voltage is below about 0.5V, while the silicon transistor excels at higher voltages. Low-load performance is especially important in applications like traction inverters because these devices operate in a low-load regime more than 85% of the time.

Fig. 1: Conduction characteristics of ICeGaN – IGBT combo device.[1]

SiC and GaN also complement each other well. Researcher Ji Shu and his colleagues at the Hong Kong University of Science and Technology mounted a low voltage e-mode GaN HEMT face-to-face with a high voltage SiC Junction field effect transistor (JFET) The resulting two-stage cascode device combines the best qualities of both materials. GaN’s high mobility improves switching speed and reduces device resistance, while the short interconnect between the two transistors minimizes parasitic losses.[⁠2]

Fig. 2: Schematic (a) and structure (b) of GaN HEMT/SiC JFET cascode device.[2]

Another cascode device, demonstrated by Umesh Mishra, dean of the college of engineering at UC Santa Barbara, and his colleagues, uses a GaN HEMT as the high voltage portion of the switch. Mishra argued that GaN on sapphire substrates improve device quality and isolation. Paired with a low-voltage silicon FET, the device achieved a high voltage rating up to 1,200V, while carrying current up to 170A.[^⁠3]

Better breakdown voltage from lateral GaN
Scaling GaN devices to higher voltage applications will require better breakdown performance and improved device capacitance. Breakdown performance is partly dependent on material quality, as defects can form a current path through the material. Still, device structure also plays an important role. For example, Sirui Feng and colleagues at the Hong Kong University of Science and Technology explained that conventional p-GaN enhancement-mode HEMTs are vulnerable to voltage transients. They added a silicon-doped n-GaN layer, connected to an extrinsic gate layer. High voltage depletes carriers from this semiconducting gate, preventing current flow in the 2DEG. This device survived 500 microsecond gate transients of up to 1,500V.[⁠4]

Another lateral HEMT design, demonstrated by Junjie Yang and colleagues at Peking University, uses alternating stripes of p-GaN and 2DEG material to build a super-junction. It behaves as a series of connected 2DEG regions. This design produces a more uniform electric field, effectively increasing the breakdown voltage for a given device area. Indeed, the breakdown voltage exceeded the 10kV limit of their test system.[^⁠5]

Fig. 3: Super-junction GaN HEMT. Bias applied to the p-GaN pillars controls the behavior of the 2DEG, and therefore the flow of current.[5]

Vertical devices put more power in less space
Increasing the current through a power device generally means increasing its physical size in order to maintain an acceptable power density. Materials with a higher breakdown voltage can make smaller devices because they can tolerate higher power density. However, the spacing between devices is still constrained by the need for adequate isolation. Vertical device architectures allow designers to maintain the separation between adjacent devices while reducing the overall circuit footprint.

Researcher Xinyi Wen and colleagues at Stanford University and Kyocera proposed a wrap-around gate current aperture vertical electron transistor (WG-CAVET). It uses a groove structure to improve electrostatic control by allowing the gate to wrap around the 2DEG channel. Reducing the groove spacing causes the depletion regions along the groove sidewalls to overlap, pinching off the 2DEG in the off state. Adding repetitions of this basic structure allows the device to scale to higher current as needed.[⁠6]

Another vertical design, proposed by Panasonic staff engineer Naoki Torii and his colleagues, incorporates a shield structure into a conventional GaN JFET, reducing parasitic capacitance. By reducing the electric field at the channel, this device achieved a breakdown voltage higher than 900V with a 57A maximum drain current. The reduced capacitance also nearly doubled the switching speed relative to a conventional design.[^⁠7]

Fig. 4: Conventional (a) and proposed (b) vertical GaN JFET structures. The shield structure in (b) offsets the gate and drain, reducing device capacitance.[7]

While silicon crystals are cubic, GaN crystals have a wurtzite (see figure 5) structure. When grown on silicon or sapphire, the c-plane of GaN lies parallel to the growth substrate. The crystal direction has a dramatic effect on the device properties. A vertical MOSFET design, presented by Toyota research domain leader Kenji Ito and colleagues, exploits the orientation-dependent properties of the material, with current flowing in the m-plane rather than the c-plane. This design is especially interesting for electric vehicle and aerospace applications, as the m-plane threshold voltage is relatively independent of ambient temperature. The use of an AlN interlayer minimized interface traps, resulting in effective mobility of more than 180 cm²/V-sec.[^⁠8]

Fig. 5: Hexagonal Wurtzite structure of gallium nitride showing major crystal planes.[⁠9]

Silicon device designers have long relied on precise placement of dopants to control both electron and hole transport. The dependence of GaN devices on the 2DEG, and therefore on the formation of GaN/AlGaN interfaces, significantly constrain device designs. Nonetheless, as these examples show, complex material stacks can be used to achieve a wide range of electrical structures.

References

1. F. Udrea, “Combo ICeGaN: The Combination of a Smart GaN HEMT and an IGBT,” 2024 International Electron Devices Meeting (IEDM), San Francisco, CA, USA, Paper 33.5
2. Ji Shu, et al., “Stacked Strongly Coupled GaN/SiC Cascode Device with Fast Switching and Reclaimed Strong dv/dt Control,” 2024 International Electron Devices Meeting (IEDM), San Francisco, CA, USA, Paper 25.1
3. U. K. Mishra, et al., “The Future of GaN is also High Voltage, High Current, and Bidirectional,” 2024 International Electron Devices Meeting (IEDM), San Francisco, CA, USA, Paper 33.3
4. Sirui Feng, et al., “An All-GaN Semiconducting-Gate HEMT for Inherent Gate-Level High-Voltage Protection and Synchronous Switching with Photoelectrically Enhanced Conductivity,” 2024 International Electron Devices Meeting (IEDM), San Francisco, CA, USA, Paper 40.6
5. Junjie Yang, et al., “10-kV E-mode GaN Lateral Superjunction Transistor,” 2024 International Electron Devices Meeting (IEDM), San Francisco, CA, USA, Paper 25.3
6. X. Wen, et al., “Wrap-Around Gate delivering 600V/1.0 mΩ∙cm², Normally-Off, Dispersion-Free CAVETs with Record-High Gate Swing,” 2024 International Electron Devices Meeting (IEDM), San Francisco, CA, USA, Paper 40.5
7. Naoki Torii, et al., “Low RonCrss Normally-off Vertical GaN Transistor on GaN Substrate Using p-GaN Shield Structure for High-Power and High-Speed Switching,” 2024 International Electron Devices Meeting (IEDM), San Francisco, CA, USA, Paper 25.2
8. Kenji Ito, et al., “High channel mobility and stable E-mode operation in AlSiO/AlN/m-plane p-type GaN MOSFETs with little temperature dependence of the threshold voltage,” 2024 International Electron Devices Meeting (IEDM), San Francisco, CA, USA, Paper 40.1
9. Lorenz, K. Ion Implantation into Nonconventional GaN Structures. Physics 2022, 4, 548-564. https://doi.org/10.3390/physics4020036

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