Industry Road Map Under Construction

While most engineers think in terms of PPA—the classic power, performance and area tradeoffs—their bosses tend to see the world in terms of risk vs. opportunity. Until 22nm, these two objectives moved forward at roughly the same pace, despite the growing technical challenges of fitting more functionality into an SoC.

Much has changed since then, and even more will change over the next few years. Risks are rising, returns are increasingly uncertain, and while there are many options for improving power and performance, most of them are either comparatively untested or completely new.

Risk is a function of a number of factors. Business schools associate it with returns on invested capital, but in the semiconductor industry it needs to be viewed technologically, as well. One of the key reasons the industry has been so successful is the ability to control technical risks, primarily through the application of and . Scaling until 22nm was rather straightforward, and it yielded both performance and power improvements as well as economic benefits. After that, designing chips required double patterning, 3D transistors to control leakage, or new substrate materials such as FD-SOI.

Semiconductor design gets far more complicated after 22nm, with more factors to consider at each new node. As the leading edge of design moves to 7nm and 5nm, scaling doesn’t yield obvious power or performance benefits, and the economic benefits become even less obvious due to the need for new equipment—particularly in the areas of inspection, metrology and lithography—as well as new transistor types, new materials, and new development tools to deal with everything from reduced noise margins and other electrical and physical effects to the introduction of quantum effects. Technical risk is increasing, and it’s not because experts don’t understand the ramifications of what they’re doing. Much of what’s being developed now has been in some state of development for years—sometimes decades. But getting that technology to work, and fine-tuning processes over billions of chips, are two entirely different things.

Adding more dimensions to design in terms of interposers and bridges, changing the structures of finFETs, and adding new materials or using them in different ways is challenging. As a whole they create changes in the supply chain of everything from where materials are obtained to who does what and in what order. Known good die issues have never been adequately resolved, which is why the first ventures in advanced packaging are being done in-house by companies such as IBM, AMD, Intel, Huawei and Marvell.

On top of that, design goals will change as the Internet of Everything kicks into gear. Chips will need to be customized in smaller batches, developed quickly and cheaply, and reuse of both software and IP will need to increase. All of these are risk factors in an industry that has been built on yields that are in excess of 80% for price-resilient markets, and well into the 90% range for price-sensitive markets.

At some point PPA will have to converge with risk/reward again. Economics need to align with technical requirements for the semiconductor industry to move forward seamlessly and quickly. When exactly that happens is anyone’s guess, and there will be a lot of churn and disruption before the industry zeroes in on one or more paths that make the most sense. Until then, companies will continue to reposition themselves through acquisitions and spinoffs, new approaches will be adopted or discarded, and many more options will be studied, tested and analyzed in extremely fine detail before the path forward is clear. Until then, the semiconductor industry’s road map will remain under construction, and as everyone who has driven a car well knows, road construction can be frustrating at times, with detours and revisions to plans, even if the final product is usually much better.