Litho Roadmap Remains Cloudy

EUV heats up for 7nm, maybe earlier, but other next-generation lithography options are on the table, as well; 450mm wafer sizes may complicate the transition.


By Mark LaPedus
For some time, the lithography roadmap has been cloudy. Optical lithography has extended much further than expected. And delays with the various next-generation lithography (NGL) technologies have forced the industry to re-write the roadmap on multiple occasions.

Today, there is more uncertainty than ever in lithography. Until recently, for example, leading-edge logic chipmakers have been planning to extend 193nm immersion with multiple patterning to the 14nm and 10nm nodes. This is because the leading NGL candidate—extreme ultraviolet (EUV) lithography—remains delayed and isn’t ready for 10nm.

But in a recent and surprise move, Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC) now plans to insert EUV at 10nm, according to Pacific Crest Securities, even though there are still many challenges with the technology. For that reason, Intel, GlobalFoundries and others are maintaining their respective lithography roadmaps and will continue to target EUV for 7nm. In addition, the other NGLs—such as directed self-assembly (DSA), maskless and nano-imprint—are still in the hunt at advanced nodes.

Adding more uncertainty to the lithographic roadmap are apparent delays with the migration toward the next-generation 450mm wafer size. Intel, according to Pacific Crest Securities, has pushed out 450mm beta equipment deliveries to about the end of 2015, which is a delay of about three quarters.

Uncertainties with NGL and the 450mm wafer transition present a multitude of challenges for chipmakers and fab tool vendors alike. It also adds more confusion in an already cloudy landscape in lithography. “It’s getting very foggy,” said Pawitter Mangat, senior manager and deputy director for EUV lithography at GlobalFoundries.

Moving targets
For years, there have been fears that optical lithography would run out of gas, prompting the need for an NGL technology. Today, however, 193nm lithography continues to churn out wafers, while NGL remains delayed. In logic, for example, the current school of thought is to use 193nm immersion with multiple patterning at 10nm. But chipmakers are begging for EUV, because the technology brings the industry back to single exposure.

To accelerate the development of EUV and 450mm, Intel, Samsung and TSMC recently invested in ASML. ASML’s first production EUV scanner, the NXE:3300B, will ship in 2013. The 300mm tool has demonstrated images down to 9nm in the lab, but EUV has encountered several delays due to problems with the power source, photomask and resists.

Unfazed by the ongoing issues, TSMC hopes to insert EUV at 10nm. The move represents a change in strategy, as TSMC was expected to use optical lithography at that node. “ASML is making progress with its EUV platform, and we believe TSMC is now committing to several tools for its 10nm ramp in 2016,” said Weston Twigg, an analyst with Pacific Crest Securities. “We believe other logic and foundry companies remain uncommitted with respect to the timing of EUV adoption.”

To put EUV in production at 10nm, TSMC must obtain the NXE:3300B and iron out the bugs at least two to three years before the process moves into production. In a short time frame, ASML and TSMC must prove the NXE:3300B is reliable, production-worthy and cost-effective.

Even with the limitations of EUV today, ASML believes the technology still can process one or two critical layers at 10nm, thereby providing a cost advantage over multiple patterning. “At 10nm, EUV can reverse the increase of process costs,” said Kurt Ronse, director of the advanced patterning department at Imec, one of ASML’s EUV tool beta sites. “At 7nm, the effect would even be more dramatic. But is EUV ready to step up?”

TSMC, of course, could change its strategy if EUV suffers another setback. Other chipmakers are aware of TSMC’s plans, but many are skeptical that EUV will be ready in time for 10nm. “I think it will be a challenge to insert EUV at 10nm,” said GlobalFoundries’ Mangat. “7nm is more realistic.”

Meanwhile, for some time, Intel has been planning to extend 193nm immersion down to its 11nm node. Using 193nm immersion, the chip giant is looking at quintuple exposure at 11nm. Intel is evaluating several NGL technologies for its 7nm node, but EUV is the leading candidate. “7nm is the likely insertion point (for EUV),” said Janice Golda, director of lithography capital equipment development at Intel. “We are all anxiously waiting for EUV.”

As before, the big problem is the power source. In the most recent update, ASML has demonstrated 40 Watts and 50 Watts of EUV power in 20-hour run times. A 55-Watt source translates to an overall EUV tool throughput of 43 wafers per hour (wph). To make EUV feasible, however, Golda said the EUV source must generate at least 80 Watts of power. This translates to an overall EUV throughput of about 58 wph. “80 Watts is everyone’s major milestone,” Golda said. “That’s the magic number.”

Another challenge is the EUV mask infrastructure. An EUV mask must be defect-free in the production process, but the industry is struggling to achieve these goals. For example, to make an EUV mask, the first step is to obtain the raw glass material or substrate. Some 70% of all phase defects on an EUV mask can be traced back to the glass alone.

This is even before the EUV mask itself goes through the production process. “For the EUV mask, the number one problem is still defects,” said Banqiu Wu, principal member of the technical staff and chief technology officer for the Mask and TSV Etch Division at Applied Materials. “The real question is how to control the phase defect number. A number of them come from the substrate. If we can’t control the substrate pits, that means we can’t overcome the challenges.”

That’s just the tip of the iceberg. The EUV mask production process is also challenging and expensive. And many of the inspection tools are not ready. “The other challenge is defect inspection,” Wu said.

There are other issues, as well. If or when EUV goes into production, the technology is initially targeted for contact-hole shrinks. “The biggest problem at the contact-hole level is so-called local CD uniformity, which is reaching numbers in the order from 1nm to 2nm one sigma, compared to the dimension that has to be printed,” said Imec’s Ronse.

The local CD uniformity numbers are still too high for the NXE:3300B, he said. To solve the problem, lithographers could use slower resists or boost the image contrast. In another solution, Imec is exploring a post-processing etch step, which enables a 30% improvement in contact-hole shrinkage.

450mm quagmire
If that isn’t enough to deal with, chipmakers and fab tool vendors must now revamp their roadmaps and reach for the reset button for 450mm. “We believe that Intel officially delayed its expectations for 450mm beta equipment deliveries by at least three quarters from 1Q ’15,” said Pacific Crest’s Twigg. “The reason for the delay likely stems from a lack of alignment with Samsung and TSMC on the timing of 450mm fabs.”

Still, the push-out merely delays the inevitable migration to 450mm fabs, which are still expected to appear in 2018 to 2020, Twigg said. When 450mm happens, the lithography contenders include 193nm and multiple patterning, EUV, and multi-beam. DSA is more of a complementary patterning scheme.

Presently, ASML is developing two wavelengths, EUV and 193nm immersion, for both the 300mm and 450mm wafer sizes. Generally, the industry wants ASML to develop its 300mm EUV tool first and then worry about 450mm later, prompting fears that ASML’s 450mm roadmap could slip. ASML itself is worried about R&D costs and return-on-investment for 450mm. “We are concerned about the lack of momentum for 450mm,” said Martin van den Brink, president and chief technology officer at ASML, at a recent event.

On its 450mm roadmap, ASML plans to ship its beta EUV tool in 2015 and a 193nm immersion system in 2016. A production 450mm EUV scanner is due out in 2018. A 450mm EUV tool is expected to be an expensive solution with a questionable throughput. A 300mm tool has a throughput of about 250 wph, while a 450mm system can run 100 to 125 wph at 1.1x the cost, according to ASML.

To hedge its bets, one industry group—the Global 450mm Consortium (G450C)—is funding Nikon to develop a 193nm immersion scanner for 450mm fabs. Nikon plans to ship “early learning tools” by 2015. “As we have said, we will be shipping to meet customer orders in 2015,” said Hamid Zarringhalam, executive vice president at Nikon Precision. “High-volume manufacturing tool shipment timing will continue to be synchronized with customer requirements.”

By then, other NGL technologies could be ready for prime time, including multi-beam direct-write. “We are prepared to insert at the 10nm node,” said David Lam, chairman of MultiBeam, a multi-beam tool startup. “Our throughput for 450mm wafers is the same as for 300mm wafers.”

KLA-Tencor, Mapper Lithography and others are also developing multi-beam tools. The industry is also pursuing DSA. And, of course, there is EUV. Still, what gets inserted down the line depends upon several factors. “The options are still being finalized. We have to look at the cost-of-ownership,” concluded GlobalFoundries’ Mangat.

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