Manufacturing Bits: Dec. 23

Gallium oxide transistors; gallium oxide on SiC and silicon.


Gallium oxide transistors
At the recent IEEE International Electron Devices Meeting (IEDM), Cornell University and Hosei University presented a paper on a gallium oxide vertical transistor with a record breakdown voltage.

Crystalline beta gallium oxide is a promising wide bandgap semiconductor material, which is used for power semiconductor applications. Gallium oxide has a large bandgap of 4.8–4.9 eV with a high breakdown field of 8 MV/cm. The technology has a high voltage figure of merit, which is more than 3,000 times greater than silicon, more than 8 times greater than silicon carbide (SiC) and more than 4 times greater than that of gallium nitride (GaN).

The technology is still in its infancy. “Despite promising advancements, the present Ga2O3 power transistors face two main challenges,” said W. Li of Cornell University in a paper at IEDM. “First, the effective channel mobility is much lower than that in the bulk. In, but not restricted to, vertical fin transistors, the effective channel mobility is found to be hampered by etch damage and sidewall depletion due to interface-trapped charge, resulting in an effective channel mobility of only 30 cm2/Vs. Second, the very high-field operation required for achieving high performance Ga2O3 devices post challenges on electric-field management.”

At last year’s IEDM, Cornell and others presented a paper on a beta gallium oxide, vertical-trench Schottky barrier diode technology.

At this year’s event, Cornell and Hosei demonstrated what it said is a record-high performance in normally-off single and multi-fin gallium oxide vertical power transistors.

To date, lateral transistors with a breakdown voltage up to 2.32 kV have been achieved. For high-voltage applications, though, vertical devices are preferred, according to researchers. Cornell and Hosei have devised a vertical device with a record breakdown voltage of 2.66 kV.

In vertical devices, the drain is on the bottom of the device, while the source is on top. On the drain, there is a gallium oxide substrate. A 10μm gallium oxide drift layer is grown on the substrate using a halide vapor phase epitaxy process.

On the top of the device, the vertical fin transistors have multiple fins. Fin channel widths were 0.15-0.45μm with pitch sizes ranging from 1.2μm to over 2μm were designed.

For this, researchers demonstrated an improved fin channel mobility with a post-deposition annealing in normally-off single-fin transistors. “The effective channel mobility is improved up to ~130 cm2/Vs with a post-deposition annealing process,” Li said. “With a fin-channel width of 0.15μm, true normally off operation is achieved with a threshold voltage of >1.5 V; a record-high breakdown voltage of 2.66 kV (at Vgs=0 V) and a specific on-resistance of 25.2 mWcm2 are obtained in multi-fin devices, corresponding to a Baliga’s figure-of-merit of 280MW/cm2, which is the highest among all Ga2O3 transistors.”

Gallium oxide on SiC and silicon
Also at IEDM, a group presented a paper on the integration of gallium oxide materials on SiC and silicon substrates.

In one demonstration, researchers integrated 2-inch gallium oxide thin films onto 4H-SiC and silicon substrates using an ion-cutting process.

The resulting devices were gallium oxide MOSFETs. The heterogeneous wafers demonstrated high thermal stability up to the ambient temperature (Tamb) of 500 K.

Gallium oxide is promising, but it suffers from a low thermal conductivity. This in turn limits its use in high-power applications.

“Heterogeneous integration of high-quality β-Ga2O3 thin films onto the high-thermal-conductivity substrates has been regarded as a promising method to overcome the thermal limitation of Ga2O3 electronics. However, due to the large lattice mismatch, the quality of β-Ga2O3 thin film synthesized by heteroepitaxy growth on foreign substrates is still not acceptable,” said Wenhui Xu of the Shanghai Institute of Microsystem and Information Technology, the Chinese Academy of Sciences (CAS), in the paper.

CAS, Xidian University, Meisei University and Virginia Polytechnic Institute and State University also contributed to the work.

The ion-cutting process solved the lattice mismatch problem. “Three high-quality heterogeneous wafers, the Ga2O3-on-SiC (GaOSiC), Ga2O3-Al2O3-SiC (GaOISiC), and Ga2O3-Al2O3-Si (GaOISi) are fabricated, which have surface RMS roughness below 0.5nm and the FWHM of XRD rocking curve of 130 arcsec,” Xu said in the paper.

“By varying the channel thickness, both enhancement- and depletion mode MOSFETs are realized on GaOSiC wafer. As the ambient temperature increases from 300 K to 500 K, little degradation is observed in the on-resistance, forward saturation current, reverse leakage current and breakdown voltage (Vbr) of the fabricated Ga2O3 MOSFETs,” Xu said. “A device Vbr above 600 V is achieved at 500 K with a weak dependence on temperature. These results show a significantly improved device thermal stability compared to the reported Ga2O3-on-Ga2O3 devices. The technology demonstrated in this work is promising to overcome the fundamental thermal limitation of Ga2O3 electronics for high-power applications.”

Leave a Reply

(Note: This name will be displayed publicly)