New Transistor Types Vs. Packaging

Plans are being formulated for the rollout of multiple types of gate-all-around FETs and literally dozens of advanced packaging options. The question now is which ones will achieve critical mass, because there aren’t enough chips in the world to support all of them profitably.

FinFETs, which were first introduced by Intel at 22nm, are running out of steam. While they will survive 10/7nm, and maybe even 7/5nm, static leakage is becoming an issue again, and the ability to manufacture increasingly taller fins has proved to be an unworkable strategy. What comes next remains to be seen, because the costs of developing gate-all-around nanosheets or horizontal or vertical nanowires is expensive. It’s expensive for the companies designing chips, but it’s especially costly for the foundries that have to buy the equipment to manufacture them.

And this is where the semiconductor industry is sitting right now. It’s overlooking a precipice, trying to figure out if it should build a bridge to the next technology, develop a different way to the next node—possibly using directed self-assembly or some other factory-grown technology such as carbon nanotube FETs—or whether it backs off entirely and pushes into one or more advanced packaging approaches. There are advantages and disadvantages to all of these approaches.

All of these approaches are expensive, and the industry cannot support all of them. In addition, all of them will cause disruption in a supply chain that has been finely tuned across decades of linear development and specialization, dating back to the days when classical scaling. So whichever paths are taken, there will be fallout.

There are couple of likely scenarios that could unfold here. First, large chipmakers could bite the bullet and push forward on scaling with new types of transistors. Samsung Foundry already has announced the introduction of nanosheet FETs at 3nm. The question is whether enough companies will follow Samsung, and whether the systems company can profitably leverage that investment for its own smart phones and other advanced electronics until it adds enough foundry customers.

It’s not clear other chipmakers are heading in that direction, however. Apple already has opted for advanced packaging, and it’s not clear that pushing to 3nm is going to actually buy a significant enough improvement in either cost or performance to warrant changing nodes every three or four years. That leaves IBM and Intel with their server chips, and both 2.5D and 3D may provide higher performance per watt and per dollar of investment than a node shrink.

This doesn’t necessarily clear things up, however. The number of options in advanced packaging is growing, rather than shrinking. Moreover, almost every advanced packaging approach, so far, has been customized for a specific application. There are efforts afoot to change that, particularly with chiplets, but so far it’s not obvious which efforts will be successful. What is clear is that advanced packaging provides some options for mixing and matching of components, with a potential in the long run for more affordable high-performance chips.

Imec, Intel, IBM, TSMC, GlobalFoundries, Samsung, UMC, and the major OSATs are all backing advanced packaging as a path forward. It may not be the only path forward, but it’s increasingly looking like a sustainable option. And there are some wild cards thrown into all of this from systems companies such as Google, Amazon, Facebook and Microsoft, which are developing their own custom chip architectures.

So what will a leading-edge chip look like in 2025? The whole industry is struggling to answer that question right now. But the longer it takes to come up with a firm answer, the more likely companies will drag their feet on new technology adoption. And that’s not good for anyone.