A study validates a way to simulate designs of electronics destined for high-stress, harsh environments.
On the example of a 28nm SRAM array, this work presents a novel reliability study which takes into account the effect of externally applied mechanical stress in circuit simulations. This method is able to predict the bit failures caused by the stress via the piezoresistive effect. The stability of each single SRAM cell is simulated using static noise margin. Finally, the whole array’s behavior is reproduced by including device parameter variations in Monte-Carlo simulations. The results show good agreement with corresponding experiments in which mechanical stress was introduced into the SRAM array by indentation. This validates the presented simulation method for future use in the design of electronic products, especially for harsh environment applications, where high stress is expected.
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