Neuro-synaptic RAM; 3D photonic-electronic data link; complex memory management.
Researchers from the National University of Singapore (NUS) and King Abdullah University of Science and Technology (KAUST) found that a standard silicon transistor can function like a biological neuron and synapse when arranged and operated in a specific way.
The team was able to replicate both neural firing and synaptic weight changes by adjusting the resistance of the bulk terminal to specific values, which allows controlling two physical phenomena taking place in the transistor: punch through impact ionization and charge trapping.
“Other approaches require complex transistor arrays or novel materials with uncertain manufacturability, but our method makes use of commercial CMOS technology,” said Mario Lanza, an associate professor in the Department of Materials Science and Engineering at NUS, in a statement. “This means it’s scalable, reliable, and compatible with existing semiconductor fabrication processes.”
To demonstrate this, the team built a two-transistor cell that can be switched between neuron or synapse operating modes. In tests, this “Neuro-Synaptic Random Access Memory,” or NS-RAM, cell demonstrated low power consumption, maintained stable performance over many cycles of operation, and exhibited consistent, predictable behavior across different devices. [1]
Researchers from Columbia University and Cornell University built a 3D photonic-electronic platform for energy-efficient, high-bandwidth data communication between spatially distinct AI compute nodes.
The chip integrates photonic devices with CMOS circuits to deliver 800 Gb/s bandwidth at 120 femtojoules per bit. With 80 photonic transmitters and receivers in a combined chip footprint of 0.3 mm2, it has a bandwidth density of 5.3 Tb/s/mm². The design is compatible with commercial CMOS fabrication on 300mm wafers. [2]
Researchers from Oak Ridge National Laboratory and the University of Tennessee created a framework to manage data more efficiently in high-performance computing memory systems that employ more complex structures, such as CXL-based multi-tier memory systems.
The Simplified Interface to Complex Memories (SICM) system automatically sorts and stores information based on need, making retrieval more efficient and enabling multiple programs with different storage needs to function within a single supercomputing rack using CXL.
“Our work is to automatically put the frequently used objects into the right location in the faster tier of memory and put the less used objects, the things that aren’t accessed as often, into the slower memory,” said Terry Jones, senior computer science researcher at ORNL, in a press release. Jones said that the approach uses sophisticated techniques to determine if certain data needs faster memory. “Imagine that within a rack of a supercomputer there’s a lot of memory, and all the nodes inside that same rack could get whatever they need from that memory. So, if inside a rack there are multiple programs, such as an AI application and a complex calculation on a small dataset, the AI program will need lots of memory, but the complex calculation will not need as much memory. Dynamically inside that rack, we could have this memory move around while those two codes are running.” [3]
[1] Pazos, S., Zhu, K., Villena, M.A. et al. Synaptic and neural behaviours in a standard silicon transistor. Nature (2025). https://doi.org/10.1038/s41586-025-08742-4
[2] Daudlin, S., Rizzo, A., Lee, S. et al. Three-dimensional photonic integration for ultra-low-energy, high-bandwidth interchip data links. Nat. Photon. (2025). https://doi.org/10.1038/s41566-025-01633-0
[3] Kammerdiener, B., Mcmichael, J.Z., Jantz, M., et al. 2025. Flexible and Effective Object Tiering for Heterogeneous Memory Systems. ACM Trans. Archit. Code Optim. 22, 1, Article 28 (March 2025). https://doi.org/10.1145/3708540
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