Converting heat to electricity; layering oxide semiconductors; controlling photonic chip temperature.
Researchers at the National Institute of Standards and Technology (NIST) and University of Colorado Boulder fabricated a device to boost the conversion of heat into electricity.
The technique involves depositing hundreds of thousands of microscopic columns of gallium nitride atop a silicon wafer. Layers of silicon are then removed from the underside of the wafer until only a thin sheet of the material remains. The interaction between the pillars and the silicon sheet slows the transport of heat in the silicon, enabling more of the heat to convert to electric current.
Once the fabrication method is perfected, the silicon sheets could be wrapped around steam or exhaust pipes to convert heat emissions into electricity that could power nearby devices or be delivered to a power grid. Another potential application would be cooling computer chips.
The method is based around the Seebeck effect, in which temperature difference induces a voltage at the junction between two different metals, causing current to flow from the hotter region to the colder one and creating a magnetic field. A material must conduct heat poorly in order to maintain a temperature difference between two regions yet conduct electricity extremely well to convert the heat to a substantial amount of electrical energy.
The researchers discovered that these properties could be decoupled in a thin membrane covered with nanopillars. They were able to reduce the heat conductivity of the silicon sheet by 21% without lowering its electrical conductivity or changing the Seebeck effect.
The team is now working on structures fabricated entirely of silicon and with a better geometry for thermoelectric heat recovery. The researchers expect to demonstrate a heat-to-electricity conversion rate high enough to make their technique economically viable for industry.
Semiconductor Thermal and Electrical Properties Decoupled by Localized Phonon Resonances: https://doi.org/10.1002/adma.202209779
Researchers from the University of Tokyo reported a deposition process for a multi-gate nanosheet oxide FET that combines high carrier mobility and reliability characteristics with normally-off operation. They focused on atomic layer deposition (ALD) of FETs with an InGaOx channel and InSnOx electrode.
The team notes that oxide semiconductors can be processed at low temperature, while still having high carrier mobility and low charge leakage, and are able to withstand high voltages. There are also advantages to using oxides rather than metals in processes where electrodes may be exposed to oxygen during the integration process and become oxidized.
However, developing the processes needed to reliably deposit very thin layers of oxide semiconductor materials in the manufacture of devices is challenging.
“Using our process, we carried out a systematic study of field effect transistors (FETs) to establish their limitations and optimize their properties,” said Kaito Hikake of the University of Tokyo. “We tuned the ratio of the components and adjusted the preparation conditions and our findings led to the development of a multi-gate nanosheet FET for normally-off operation and high reliability.”
“In rapidly moving areas such as electronics, it is important to translate proof of concept findings into industrially relevant processes,” added Masaharu Kobayashi, associate professor at the University of Tokyo. “We believe that our study provides a robust technique that can be used to produce devices that meet the market’s need for manufacturable 3D integrated circuits with high function.”
A Nanosheet Oxide Semiconductor FET Using ALD InGaOx Channel and InSnOx Electrode with Normally-off Operation, High Mobility and Reliability for 3D Integrated Devices: VLSI Symposium 2023
Researchers at Oregon State University and Baylor University are working toward reducing the energy consumption of the photonic chips used in data centers and supercomputers.
Significant energy is required to keep the temperature of photonic chips stable for best performance. The team says they’ve found a way to reduce the energy needed for temperature control by a factor of more than 1 million.
The team demonstrated gate-tuning on-chip wavelength division multiplexing (WDM) filters with large wavelength coverage for the entire channel spacing using a silicon microring resonator (Si-MRR) array driven by high mobility titanium-doped indium oxide (ITiO) gates.
“We were able to make working prototypes that show temperature can be controlled via gate voltage, which means using virtually no electric current,” said John Conley of the OSU College of Engineering.
The integrated Si-MRRs showed wavelength tunability up to 589 pm/V, or VπL of 0.050 V cm with a high-quality factor of 5200. The on-chip WDM filters, which consisted of four cascaded ITiO-driven Si-MRRs, could be continuously tuned across the 1543–1548 nm wavelength range by gate biases with near-zero power consumption.
On-chip wavelength division multiplexing filters using extremely efficient gate-driven silicon microring resonator array: https://www.nature.com/articles/s41598-023-32313-0
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