A technical paper titled “Cost-Optimized and Robust Latch Hardened against Quadruple Node Upsets for Nanoscale CMOS” was just published by researchers at Anhui University, Hefei University of Technology, Anhui Polytechnic University, Kyushu Institute of Technology, and the University of Montpellier/CNRS.
Abstract:
“With the aggressive reduction of CMOS transistor feature sizes, the soft error rate of nano-scale integrated circuits increases exponentially. In this paper, we propose a novel costoptimized and robust latch, namely CRLHQ, hardened against quadruple-node-upsets (QNUs) for nanoscale CMOS technology. The latch mainly comprises a 5×5 matrix based on interlocked source-drain cross-coupled inverters to robustly store logic values. Owing to the redundant constructed feedback loops, the latch can recover from all possible QNUs. Simulation results demonstrate all key QNUs’ recovery of the proposed CRLHQ latch. Simulation results also show that the latch can approximately reduce 44.3% D-Q delay, 7.3% silicon area and 14.2% delay-area-power product (DAPP), compared with the state-of-the-art same-type reference latch that can recover from any QNU.”
Find the technical paper here. Published August 2022.
Aibin Yan, Shukai Song, Jixiang Zhang, Jie Cui, Zhengfeng Huang, et al.. Cost-Optimized and Robust Latch Hardened against Quadruple Node Upsets for Nanoscale CMOS. ITC-Asia 2022 – IEEE International Test Conference in Asian, Aug 2022, Taipei, Taiwan. In press. fflirmm-03770182.
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