Chief Chip Architect: less process complexity; solves scaling, leakage and variability issues
ASN recently had a chance to talk to ST-Ericsson’s Chief Chip Architect Louis Tannyeres about the move to 28nm FD-SOI for smartphones and tablet SOCs. Take-away message: FD-SOI solves – with less process complexity – scaling, leakage and variability issues to further shrink CMOS technology beyond 28nm. Here’s what he said.
Louis Tannyeres, Principal Fellow, Chief Chip Architect and head of System Silicon Development at ST-Ericsson.
Advanced Substrate News (ASN): Can you give us a bit of background on the markets you’re addressing?
Louis Tannyeres (LT): Founded in 2009, ST-Ericsson is an industry leader in design, development and creation of cutting edge mobile platforms and semiconductors across the broad spectrum of wireless technologies. Today, we are actively engaged with seven of the top nine mobile device OEM manufacturers by revenue.
ST-Ericsson’s portfolio covers all market segments, with an emphasis on mid to high-range smartphones and tablets.
ASN: What are the challenges that the product designers (your clients) face with respect to available technology vs. consumer expectations?
LT: With the recent evolution in smartphone capabilities consumer expectations are rising fast. Ultra-fast multicore Gigahertz processors, stunning 3D graphics, full HD multimedia and high-speed broadband connectivity have become the norm for high-end devices.
Consumers expect these features to be delivered in a device that is slim, light and can last for at least as long as their previous phones did. For our customers, the product designers, this translates into requirements for delivering high performance at low power in a cost effective manner. FD-SOI is a technology that addresses exactly these requirements.
ASN: What advantages do you expect FD-SOI to bring to the platform?
LT: FD-SOI is a technology that is available for design today and will allow existing designs in 28nm to benefit today already from significant improvements in performance and power. FD-SOI solves – with less process complexity – scaling, leakage and variability issues to further shrink CMOS technology beyond 28nm.
ST-Ericsson's NovaThor™ family is an integrated solution for the mainstream smartphone segment, in which modems and application processors are built into a single piece of silicon. The application engine uses the latest ARM®-based multi-core CPUs optimized to deliver the highest performance and support for advanced 2D & 3D graphics cores.
ASN: How have your customers reacted to this bold move?
LT: True market disruptions are only understood after the fact. We believe FD-SOI is such a disruption and a truely differentiated solution. There is a real opportunity for a FD-SOI 28nm solution and then 20nm as a key technology differentiator. Our customers have reacted favorably to hearing that we will be enabling FD-SOI technology in our next generation of products. And since we are enabling this technology in STMicroelectronics’ foundries, we have also minimized our risk with respect to market adoption trends.
ASN: How difficult was it to port the existing design from bulk to FD-SOI?
LT: FD-SOI is a technology that is available for design today and will allow existing designs in 28nm to benefit today already from significant improvements in performance and power. Thanks to fully depleted devices, FD-SOI allows operating at fast speed at extremely low operating voltages – a key characteristic to allow low power operation for mobile devices.
A design platform developed for bulk CMOS technology can be ported to planar FD by re-characterization using planar FD SPICE models. Only a limited number of critical IPs need to be tuned or redesigned.
ASN: What was the impact on design flow?
LT: The equations describing the electrical behavior of fully depleted transistors are different from those used for conventional bulk CMOS, so designing on planar FD requires specific extraction deck and SPICE models. The model we use is now integrated in all major commercially available simulators. Apart from that, the design flows, methodologies and tools do not need any specific adaptations.
ASN: Do you foresee any major challenges in fast-ramping to high volumes?
LT: 28nm planar FD manufacturing technology has a lot of commonalities with traditional 28nm Low-Power CMOS technology and STMicroelectronics’ strategy has been to reuse as much as possible the 28nm low-power bulk CMOS process. The Back-End part of the process is a direct copy of the 28nm bulk technology. The Front-End part of the process also relies in majority on a direct re-use of equivalent process modules from the bulk technology. Only a few steps have been optimized, added or removed. Overall, the Back-End is 100% identical to the traditional 28nm bulk low-power CMOS process, and the Front-End of Line (FEOL) has 80% in common with that same process.
ASN: When do you expect to have the first prototypes available?
LT: FD-SOI will be introduced into next generation products from ST-Ericsson. At this time, our first 28nm FD-SOI products are scheduled to tape out in Q3 2012 with production start anticipated in 2013.
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