Standardizing Defect Coverage In Analog/Mixed Signal Test

A newly drafted IEEE standard will bring more consistency to defect metrics in analog/mixed (AMS) designs, a long-overdue step that has become too difficult to ignore in the costly heterogeneous assemblies being deployed inside of data centers and mobile devices.

Standardizing analog is no simple feat due to the legacy approach to AMS design, and this is not the first attempt at improving test coverage and predictability for analog circuitry. While digital circuits benefit from well-established fault models and testing methodologies, the inherent complexity and diversity of AMS designs make it difficult to develop the kind of consistency that digital designs have seen for years. Traditional digital fault models are not suitable for the nuanced behavior of analog circuits, making it difficult to compare one test approach to another, or even one chip to another in the same company.

“There’s a strong desire to do accurate defect-level modeling in the analog space because analog circuits and the impacts of defects are much more diverse,” says Ken Butler, senior director of business development at Advantest. “Stuck-at fault models are an acceptable compromise between defect accuracy and simulation performance for large digital circuits, but analog circuits present a different challenge. Even for smaller circuits, simulating defect models takes significant time. With larger circuits, it becomes impractical to run full simulations due to their complexity without resorting to methods such as mixed behavioral and switch level modeling.”

One of the major obstacles to creating a standard is the sheer variety of AMS designs and defect mechanisms. In digital circuits, fault models are closely tied to specific test methods. But analog circuits require a more flexible approach that considers a wide universe of parametric defects. Additionally, there has been no agreed-upon way to account for and communicate test coverage across different testing tools, which further complicates efforts to develop a unified standard.

“With analog ICs, you usually don’t have detailed mapping within the chip,” says Dieter Rathei, CEO of DR Yield. “If an electrical defect occurs, it often requires special investigation to pinpoint the exact physical location. Unlike memory arrays, where you might spot an optical defect immediately, analog devices typically rely on a defect map correlation rather than a bitmap correlation, which means you have less spatial accuracy. This lack of precision can force you to make some educated guesses. Maybe several defects could have caused the failure, or perhaps only one. This makes identifying the root cause, or ‘killer defect,’ a lot more challenging than with devices that provide detailed spatial resolution of the responses.”

IEEE P2427 aims to address these challenges by establishing a comprehensive framework that standardizes defect coverage calculations and testing practices for AMS circuits. However, despite its importance, the adoption of P2427 will face many hurdles. The industry’s reliance on existing, often proprietary tools and methodologies, is slowing the adoption of the standard. Additionally, the challenge of convincing design teams and executives to integrate new testing methods into their processes has been a persistent issue.

“Fault models just weren’t working for what we needed,” explained Anne Meixner, elected officer and editor of the P2427 standard (and consulting editor at Semiconductor Engineering). “Internally, companies were creating their own tools to insert defects and evaluate coverage, or they were employing commercial tools. But there has been no way to independently compare these numbers from one company to another. Especially now, with IP blocks and chiplets, there’s a need to know if the test coverage meets certain criteria. It’s evolved to the point where we need a standard for how to do the accounting.”

Tackling complexity
Testing analog and mixed-signal chips presents unique testing challenges due to their inherent complexity. Unlike purely digital circuits, AMS designs involve both analog and digital signals that must be carefully managed and tested to ensure proper function. This complexity often leads to inconsistencies in testing methods, with different manufacturers and testing facilities employing varied approaches that can result in discrepancies in test results and, ultimately, the quality of the chips produced.

“Analog has redundancy built in, and it has feedback that can cause many defects to be undetectable,” says Mayukh Bhattacharya, R&D executive director for defect/fault simulation products at Synopsys. “For example, a phase-locked loop (PLL) has a feedback loop that is forgiving. Defects may exist, but the PLL may still lock. This leads to low defect coverage, even though the chip performs well in the field.”

In addition, analog issues such as parametric defects and redundancy require more sophisticated simulation tools and techniques to accurately assess defect coverage. The new standard provides clear methods for dealing with these challenges, such as addressing the limitations of simulating one defect at a time, or considering the complexities of parametric variation that are not present in purely digital circuits.

“Analog circuit performance is inherently parametric, which implies that assessing test coverage should focus on parametric defects,” says Stephen Sunter, engineering director for mixed signal DFT for Siemens EDA, and past chair of the P2427 Working Group. “But analog circuits are designed to tolerate large deviations in process parameters, which makes it challenging to decide how much deviation is defective.”

One of the primary issues in AMS chip testing has been the lack of transparency and consistency in current practices. Without standardized definitions and procedures, it has been difficult to ensure that tests are both comprehensive and comparable across different contexts. This inconsistency can lead to significant risks, particularly as AMS chips are increasingly used in critical applications such as automotive safety systems and medical devices, where reliability is paramount.

“The challenge is that analog testing has largely been a specification-driven exercise, unlike digital testing where structural-based testing is common,” says Butler. “In analog, testing starts with the data sheet. For example, if it’s an ADC or a DAC, there might be specs for linearity, total harmonic distortion (THD), and other parameters that we directly measure. These data sheet specifications drive the test content, and there hasn’t been an effective way to measure test coverage in the same structural way as with digital circuits.”

The IEEE P2427 standard introduces standardized nomenclature and definitions, which helps to eliminate ambiguity and ensure that all parties involved in the testing process have a common understanding of the terms and procedures involved. Moreover, P2427 establishes guidelines for calculating defect coverage, a critical aspect of AMS chip testing that historically has been fraught with inconsistencies. By standardizing these calculations, P2427 ensures that defect coverage assessments are reliable and comparable across different testing environments.

“One of the major contributions of P2427 is the concept of detectable defect coverage,” says Bhattacharya. “Analog chips might show low overall coverage, but when you focus on what’s detectable you can get a more useful, higher-coverage metric. This is critical in aligning the defect universe to real-world conditions.”

This concept of the “defect universe” is central to the standard, representing the full range of potential defects that can occur in analog and mixed-signal circuits, which is crucial for understanding how defect coverage is calculated and reported. Unlike digital circuits, where a limited set of fault models can accurately capture failure modes, analog circuits are more complex due to their continuous nature and variability in performance across different operating conditions.

In P2427, the “defect universe” includes all reasonably likely defects. However, not every defect is detectable during testing. This distinction between detectable and undetectable defects is essential for providing an accurate and useful measure of defect coverage.

“Using digital fault standards to define a finite fault universe on the analog side was practically impossible,” says Amit Bajaj, product engineering director at Cadence. “This was the primary motivation to come together and determine a way that practically makes sense for the analog side of fault simulation and fault analysis. Defect models defined by the standard (opens and shorts) bring in practicality by making the defect universe a finite list. That makes a big difference, because once the defect universe can be successfully defined, the coverage can also be calculated and worked upon to improve.”

This goal is to let companies prioritize defects that are likely to impact real-world performance while avoiding an overwhelming focus on undetectable defects that may not affect functionality.

“Considering that the analog is not composed of a very reduced set of gates, like in digital, the defect simulation is the logical first step to face the coverage issues encountered in the analog world,” says Anthony Coyette, R&D manager for test automation and data analytics at Onsemi. “We have used it to optimize test programs, where the same tests would have been applied for multiple power-supplies values and multiple temperatures such as min-typ-max voltages on cold room/hot temperature for automotive. Our (lack of) returns over time have proven that defect simulations can effectively help us in removing redundant tests and get to better test times.”

Finally, the new standard emphasizes the importance of clear reporting and accounting for detected and undetected defects. It allows for justification in cases where certain defects are deemed undetectable, promoting a more comprehensive and transparent approach to analog testing.

“The P2427 standard focuses on providing a robust method for assessing defect test coverage,” says Meixner. “It introduces a metric for accounting, with recommendations on simulating multiple process corners to ensure a more thorough assessment. While it doesn’t dictate specific sampling strategies, it emphasizes the importance of clear communication regarding the approach taken. For example, if you simulate 10,000 defective circuits, the standard encourages smart sampling to estimate results with accuracy, similar to running all simulations. It requires reporting key details, such as whether a full or sampling-based approach was used, and providing error margins to clarify the confidence level in the results — such as stating there’s a 95% chance the result will be consistent within a certain range.”

Key components of P2427

• Nomenclature and Definitions: One of the core aspects of P2427 is the establishment of standardized nomenclature and definitions. This includes key terms such as “Defect Universe” and “Detectable Defects,” which are essential for ensuring that all parties involved in AMS chip testing are on the same page. The standard also provides detailed definitions of various types of defects and failure modes, helping to eliminate ambiguity and ensure that tests are both comprehensive and consistent.
• Standardized Practices: P2427 establishes standardized chip testing practices that cover a wide range of testing procedures, from initial design verification to final product testing. The standard provides guidelines on how to perform these tests, what tools and techniques should be used, and how to interpret the results. This ensures that testing is both thorough and reliable, reducing the risk of defects going undetected.
• Defect Coverage Calculation: One of the most critical aspects of AMS chip testing is defect coverage, which measures the extent to which potential defects are identified during testing. P2427 provides a standardized framework for calculating defect coverage, ensuring that these calculations are consistent and reliable. This is essential for AMS chips, where defects can have a significant impact on performance and reliability.
• Testing Methodologies: The standard outlines specific testing methodologies that are recommended for AMS chips. These methodologies are designed to be both comprehensive and efficient, ensuring that all critical aspects of the chip’s performance are tested without unnecessary duplication of effort. The standard also provides guidelines on how to select the most appropriate testing methodologies for different types of AMS chips, taking into account factors such as the chip’s complexity and intended application.

“The P2427 standard, while addressing many key areas, still leaves some challenges, particularly around the efficiency of computations during simulations,” says Meixner. “We mention sampling as a possible solution but don’t prescribe how it should be done, only that if it’s used, the methodology must be reported. The focus moving forward will be on adoption — encouraging companies to use the standard and provide feedback on what works and what’s lacking. After more than two years of revisions and a second ballot scheduled for this fall, the goal is to publish by the end of 2025. The most valuable insights will come from users, helping us understand what gaps remain and what improvements are needed.”

Impact on the industry
By establishing a standardized framework for defect modeling and test coverage, P2427 brings much-needed transparency and consistency to the testing process. One of the immediate benefits is a common language for companies to define and communicate defect coverage. By adopting this standard, companies can now demonstrate their defect coverage in a way that is comparable and universally understood, which is crucial for meeting stringent quality and safety requirements.

AMS testing often is an ad-hoc process, where companies rely on internal methods and tools that are not easily comparable across the industry. P2427 formalizes these processes, providing a clear methodology for calculating defect coverage and improving the overall accountability of AMS chip testing.

In addition, the impact of P2427 extends beyond the design and manufacturing stages, influencing relationships between semiconductor companies and their customers. With standardized defect coverage metrics, companies can more effectively communicate the reliability of their chips to customers, improving trust and transparency in business transactions. This is particularly valuable for companies that supply chips for safety- and mission-critical applications, where failures can lead to catastrophic consequences.

Moreover, the establishment of a universal testing standard can drive innovation in both test tools and design practices. As companies work to meet the requirements set forth in P2427, there may be opportunities to optimize the design for testability (DFT) in AMS circuits, leading to improvements in overall chip performance and reliability. The standard creates a foundation for ongoing advancements in AMS testing methodologies, ensuring that the industry continues to evolve in a more structured and efficient manner.

“The key takeaway from the P2427 standard is that, even if you think you have poor coverage on your chip, you now have a way to get help in terms of really filtering out the undetectable stuff,” adds Bhattacharya. “And you can justify it.”

Conclusion
P2427 marks a significant step forward in the field of AMS chip testing. By introducing standardized terminology, practices, and defect coverage calculations, it addresses many of the long-standing challenges in testing AMS chips. The complexity of analog and mixed-signal circuits has historically made it difficult to establish consistent testing protocols, leading to discrepancies in test results and potential gaps in defect detection. P2427 bridges this gap, offering a robust framework that ensures greater accuracy, consistency, and transparency across the industry.

The standard promotes a common understanding among chip designers, manufacturers, and test engineers, enabling them to communicate more effectively and make informed decisions about testing methodologies. This, in turn, will help improve the quality and reliability of AMS chips in critical applications such as automotive, medical, and consumer electronics.

“Now we have a mechanism that allows us to definitively state the defect coverage in AMS circuits,” says Butler. “This standard levels the playing field and helps ensure that every company is adhering to the same rules and practices when claiming coverage.”

Related Reading
The Future Of Fault Coverage In Chips
System-level test offers speed and lower cost, but there are limits to what it can do.