Week In Review: Manufacturing, Test

By Mark LaPedus - 31 Jul, 2020 - Comments: 0

Chipmakers and OEMs As reported, Intel this week reorganized its operations following delays with its 7nm technology. Intel is behind TSMC and Samsung in technology. As a result, TSMC’s foundry customers, such as AMD, Nvidia and others, are also pulling ahead of Intel. In addition, reports have surfaced that Intel will outsource some of its leading-edge chip production to TSMC. To solve t... » read more

Ins And Outs Of In-Circuit Monitoring

By Ed Sperling - 21 Jul, 2020 - Comments: 2

At 7nm and 5nm, in-circuit monitoring is becoming essential. Steve Crosher, CEO of Moortec, talks about the impact of rising complexity, how different use cases and implementations can affect reliability and uptime, and why measuring electrical, voltage and thermal stress can be used to statistically predict failures and improve reliability throughout a chip’s lifetime. » read more

Designing For Extreme Low Power

By Brian Bailey - 09 Jul, 2020 - Comments: 3

There are several techniques available for low power design, but whenever a nanowatt or picojoule matters, all available methods must be used. Some of the necessary techniques are different from those used for high-end designs. Others have been lost over time because their impact was considered too small, or not worth the additional design effort. But for devices that last a lifetime on a si... » read more

Power Impact At The Physical Layer Causes Downstream Effects

By Ann Mutschler - 09 Jul, 2020 - Comments: 0

Data movement is rapidly emerging as one of the top design challenges, and it is being complicated by new chip architectures and physical effects caused by increasing density at advanced nodes and in multi-chip systems. Until the introduction of the latest revs of high-bandwidth memory, as well as GDDR6, memory was considered the next big bottleneck. But other compute bottlenecks have been e... » read more

Increasing eFPGA Density

By Ed Sperling - 24 Jun, 2020 - Comments: 0

How to boost embedded FPGA density to the point where it is competitive with traditional FPGAs, at a lower cost and faster turnaround time. Geoff Tate, CEO of Flex Logix, talks about the importance of interconnects and standard cells in adding flexibility into chips, and why eFPGAs are suddenly gaining attention. » read more

China Speeds Up Advanced Chip Development

By Mark LaPedus - 22 Jun, 2020 - Comments: 18

China is accelerating its efforts to advance its domestic semiconductor industry, amid ongoing trade tensions with the West, in hopes of becoming more self-sufficient. The country is still behind in IC technology and is nowhere close to being self-reliant, but it is making noticeable progress. Until recently, China’s domestic chipmakers were stuck with mature foundry processes with no pres... » read more

How To Improve DPPM By 10X Without Affecting Yield

By Shai Eisen - 15 Jun, 2020 - Comments: 0

Chips today are under immense pressure. With wider process variation manifested at wafer and die levels in single-digit nodes, highly complex designs, and effects of application and system integration, it’s no wonder the electronics value chain is becoming ever more reliant on expensive guard-bands. The ecosystem is not yet equipped to find all existing defects during test. So while quality e... » read more

Aging Problems At 5nm And Below

By Brian Bailey - 11 Jun, 2020 - Comments: 3

The mechanisms that cause aging in semiconductors have been known for a long time, but the concept did not concern most people because the expected lifetime of parts was far longer than their intended deployment in the field. In a short period of time, all of that has changed. As device geometries have become smaller, the issue has become more significant. At 5nm, it becomes an essential par... » read more

High-Speed SerDes At 7/5nm

By Ed Sperling - 02 Jun, 2020 - Comments: 0

Manmeet Walia, senior product marketing manager at Synopsys, talks with Semiconductor Engineering about how to optimize PHYs for integration on all four corners of an SoC, as well as the PPA implications of moving large amounts of data across and around a chip. » read more

Ensuring HBM Reliability

By Ed Sperling - 27 May, 2020 - Comments: 0

Igor Elkanovich, CTO of GUC, and Evelyn Landman, CTO of proteanTecs, talk with Semiconductor Engineering about difficulties that crop up in advanced packaging, what’s redundant and what is not when using high-bandwidth memory, and how continuous in-circuit monitoring can identify potential problems before they happen. » read more

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Knowledge Centers
Entities, people and technologies explored

Intel Vs. Samsung Vs. TSMC

Foundry competition heats up in three dimensions and with novel technologies as planar scaling benefits diminish.

by Ed Sperling

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

Legacy Process Nodes Going Strong

The critical, and growing, significance of mature node chips and processes.

by Bryon Moyer

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

Chip Industry Week In Review

Softbank's acquisition; advanced packaging funding; glass substrates; engineered copper wire; semi equipment set new record; HBM4; AI chips rake in funding; X-ray inspection; apprenticeships.

by The SE Staff

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

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