More Memory And Processor Tradeoffs


Creating a new chip architecture is becoming an increasingly complex series of tradeoffs about memories and processing elements, but the benefits are not always obvious when those tradeoffs are being made. This used to be a fairly straightforward exercise when there was one processor, on-chip SRAM and off-chip DRAM. Fast forward to 7/5nm, where chips are being developed for AI, mobile ph... » read more

Low Power Meets Variability At 7/5nm


Power-related issues are beginning to clash with process variation at 7/5nm, making timing closure more difficult and resulting in re-spins caused by unexpected errors and poor functional yield. Variability is becoming particularly troublesome at advanced nodes, and there are multiple causes of that variability. One of the key ones is the manufacturing process, which can be affected by every... » read more

The 7nm Pileup


The number of 7nm designs is exploding. Cadence alone reports 80 new 7nm chips under design. So why now, and what does this all mean? First of all, 7nm appears to be the next 28nm. It's a major node, and it intersects with a number of broad trends that are happening across the industry, all of which involve AI in one way or another. The big question now is how many of them will survive long ... » read more

Billion-Gate Design Connectivity


Sasa Stamenkovic, senior field application engineer at OneSpin Solutions, explains how to find and resolve connectivity issues in integrating large numbers of components in very big designs, often at the leading edge nodes and in markets such as AI. » read more

Improving SAQP Patterning Yield Using Virtual Fabrication And Advanced Process Control


Advanced logic scaling has created some difficult technical challenges, including a requirement for highly dense patterning. Imec recently confronted this challenge, by working toward the use of Metal 2 (M2) line patterning with a 16 nm half-pitch for their 7nm node (equivalent to a 5nm foundry node). Self-Aligned Quadruple Patterning (SAQP) was investigated as an alternative path to Extreme Ul... » read more

Single Vs. Multi-Patterning EUV


Extreme ultraviolet (EUV) lithography finally is moving into production, but foundry customers now must decide whether to implement their designs using EUV-based single patterning at 7nm, or whether to wait and instead deploy EUV multiple patterning at 5nm. Each patterning scheme has unique challenges, making that decision more difficult than it might appear. Targeted for 7nm, single pattern... » read more

Virtual Fabrication And Advanced Process Control Improve Yield For SAQP Process Assessment With 16nm Half-Pitch


This paper uses Virtual Fabrication to assess the Imec 7nm node (iN7) Self-Aligned Quadruple Patterning (SAQP) integration scheme for the 16nm half-pitch Metal 2 line formation. We first present the technical challenge of obtaining defect-free M2 lines with SAQP, and then provide a solution to achieve a » read more

EUV Mask Readiness Challenges


Semiconductor Engineering sat down to discuss extreme ultraviolet (EUV) lithography and photomask technologies with Emily Gallagher, principal member of the technical staff at Imec; Harry Levinson, principal at HJL Lithography; Chris Spence, vice president of advanced technology development at ASML; Banqiu Wu, senior director of process development at Applied Materials; and Aki Fujimura, chief ... » read more

Timing Is Of The Essence


Today's advanced 16/7nm system-on-chips (SoCs) are faced with increased variation as they push for lower power. While the sizes of the transistors continue to shrink following Moore's Law, the threshold voltages fail to scale. This causes wide timing variability leading to timing closure difficulties, design re-spins and poor functional yield. Learn how ANSYS Path FX with its unique variatio... » read more

How To Build An Automotive Chip


The introduction of advanced electronics into automotive design is causing massive disruption in a supply chain that, until very recently, hummed along like a finely tuned sports car. The rapid push toward autonomous driving has changed everything. This year, Level 3 autonomy will begin hitting the streets, and behind the scenes, work is underway to design SoCs for Level 4. But how these chi... » read more

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