tag: Cadence

CXL: The Future Of Memory Interconnect?
By Karen Heyman - 12 Oct, 2023 - Comments: 1

Momentum for sharing memory resources between processor cores is growing inside of data centers, where the explosion in data is driving the need to be able to scale memory up and down in a way that roughly mirrors how processors are used today. A year after the CXL Consortium and JEDEC signed a memorandum of understanding (MOU) to formalize collaboration between the two organizations, suppor... » read more

Understand The Physics Of Re-Entry Vehicles Using Numerical Modeling And Simulation
By Veena Parthan - 12 Oct, 2023 - Comments: 0

In the early years of space exploration, scientists and engineers dreamed of sending vehicles to Mars that could land on the planet's surface and explore its terrain. However, one of their biggest challenges was safely reentering the Martian atmosphere. Many early attempts at Mars missions failed because the vehicles either burned up during re-entry or crashed onto the surface. However, as tech... » read more

Blog Review: October 11
By Jesse Allen - 11 Oct, 2023 - Comments: 0

Cadence's Sangeeta Soni examines Integrity and Data Encryption (IDE) verification considerations for Compute Express Link (CXL) devices, including MAC generation and handling, key programming and exchange, and early MAC termination. Synopsys' Madhumita Sanyal points to how the increased bandwidth of PCIe 6.0 supports the demanding requirements of AI accelerators. Siemens' Kevin Webb expla... » read more

Chip Industry Week In Review
By The SE Staff - 06 Oct, 2023 - Comments: 0

By Jesse Allen, Liz Allan, and Gregory Haley A potential government shutdown beginning in November would be "massively disruptive" for the Commerce Department as it continues to disburse critical funding featured in the CHIPS Act to boost semiconductor research and development in the U.S., according to Secretary Gina Raimondo. Global semiconductor industry sales totaled $44 billion in Aug... » read more

Making Sensors More Reliable
By Karen Heyman - 05 Oct, 2023 - Comments: 0

Experts at the Table: Semiconductor Engineering sat down to talk about the latest issues in sensors with Prakash Madhvapathy, director of product marketing, Tensilica audio/voice DSPs group at Cadence; Kevin Hughes, senior product manager for MEMS sensors at Infineon; and Matthew Hogan, product management director at Siemens EDA. What follows are excerpts of that conversation. [L-R] Kevin ... » read more

Gearing Up For Level 4 Vehicles
By John Koon - 05 Oct, 2023 - Comments: 0

More autonomous features are being added into high-end vehicles, but getting to full autonomy will likely take years more effort, a slew of new technologies — some of which are not in use today, and some of which involve infrastructure outside the vehicle — along with sufficient volume to bring the cost of these combined capabilities down to an affordable price point. In the meantime, ma... » read more

Software Stack For Edge AI Performance
By Suhas Mitra - 05 Oct, 2023 - Comments: 0

Developing an agile software stack is important for successful AI deployment on the edge. We regularly encounter new machine learning models created from multiple AI frameworks that leverage the latest primitives and state-of-the-art ML model topologies. This Cambrian explosion has resulted from a fertile open-source community that has embraced AI and is now fueling a wide proliferation of ML m... » read more

Blog Review: October 4
By Jesse Allen - 04 Oct, 2023 - Comments: 0

Cadence's Felipe Goncalves checks out the Integrity and Data Encryption (IDE) feature in PCIe 6.0, a new layer inserted between the transection layer and data link layer with the goal of protecting against threats from physical attacks on the link. Siemens' Robin Bornoff, Daniel Berger, and Kai Liu explore the potential for large language models (LLMs) make the use of CAE tools simpler, more... » read more

Everyone’s A System Designer With Heterogeneous Integration
By Ann Mutschler - 02 Oct, 2023 - Comments: 0

The move away from monolithic SoCs to heterogeneous chips and chiplets in a package is accelerating, setting in motion a broad shift in methodologies, collaborations, and design goals that are felt by engineers at every step of the flow, from design through manufacturing. Nearly every engineer is now working or touching some technology, process, or methodology that is new. And they are inter... » read more

Chip Industry Week In Review
By The SE Staff - 29 Sep, 2023 - Comments: 0

By Susan Rambo, Liz Allan, and Gregory Haley. TSMC rolled out the second version of its 3Dblox, which creates an infrastructure for stacking chiplets and other necessary components in a package, along with a standardized way of achieving that. Two novel features are chiplet mirroring for design reuse, and what is basically sandbox for power and thermal analysis of different design elements. ... » read more

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