AI Testing: Pushing Beyond DFT Architectures


Every day, more applications are deploying artificial intelligence (AI) system to increase automation beyond traditional systems. The continuous growth in computing demands of AI systems require designers to develop massive, highly parallel AI processor chips. Their large sizes and types of applications have a significant impact on their design and test methodologies. With thousands of repeated... » read more

Merging Verification And Test


While the disciplines of functional verification and test serve different purposes, their histories were once closely intertwined. Recent safety and security monitoring requirements coupled with capabilities being embedded into devices is bringing them closer together again, but can they successfully cooperate to bring about improvements in both? Getting there may be difficult. Three phases ... » read more

What Is Silicon Lifecycle Management? A Strategic Imperative


The recent buzz about silicon lifecycle management speaks to the boom in high-stakes electronic devices. Whether it is an SoC used in a vehicle or in the datacenter, there are compelling reasons to monitor and analyze data regarding the design, realization, deployment, and field service of the device. While silicon lifecycle management is an emerging paradigm in the semiconductor industry, i... » read more

Demand for IC Resilience Drives Methodology Changes


Applications that demand safety, security, and resilience are driving new ways of thinking about design, verification, and the long-term reliability of chips on a mass scale. The need is growing for chips that can process more data faster, over longer periods of time, and often within a shrinking power budget. That, in turn, is forcing changes at multiple levels, at the architecture, design,... » read more

Hunting For Open Defects In Advanced Packages


Catching all defects in chip packaging is becoming more difficult, requiring a mix of electrical tests, metrology screening, and various types of inspection. And the more critical the application for these chips, the greater the effort and the cost. Latent open defects continue to be the bane of test, quality, and reliability engineering. Open defects in packages occur at the chip-to-substra... » read more

Designing 2.5D Systems


As more designs hit the reticle limit, or suffer from decreasing yield, migrating to 2.5D designs may provide a path forward. But this kind of advanced packaging also comes with some additional challenges. How you adapt and change your design team may be determined by where your focus has been in the past, or what you are trying to achieve. There are business, organizational, and technical c... » read more

Preventing Chips From Burning Up During Test


It’s become increasingly difficult to manage the heat generated during IC test. Absent the proper mitigations, it’s easy to generate so much heat that probe cards and chips literally can burn up. As a result, implementing temperature-management techniques is becoming a critical part of IC testing. “We talk about systems, saying the system is good,” said Arun Krishnamoorthy, senior... » read more

Design Issues For Chips Over Longer Lifetimes


Semiconductor Engineering sat down to discuss the myriad challenges associated with chips used in complex systems over longer periods of time them with Jean-Marie Brunet, senior director for the Emulation Division at Siemens EDA; Frank Schirrmeister, senior group director for solution marketing at Cadence; Maurizio Griva, R&D Manager at Reply; and Laurent Maillet-Contoz, system and architec... » read more

Automotive Test Moves In-System


With the electrification of automobiles, it’s not enough to test the new electronics thoroughly at the end of the manufacturing process. Safety standards now require that tests be performed live, in the field, with contingency plans should a test fail. “We see clear demand from the automotive semiconductor supply chain for design functionality specifically aimed at in-system monitoring,�... » read more

Have It All With No-Compromise DFT


The dramatic rise in manufacturing test time for today’s large and complex SoCs is rooted in the use of traditional approaches to moving scan test data from chip-level pins to core-level scan channels. The pin-multiplexing (mux) approach works fine for smaller designs but can become problematic with an increase in the number of cores and the design complexity on today’s SoCs. The next revol... » read more

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