Like Wayne Gretzky, EDA Aims To Be Where The Puck Is Going, Not Where It Has Been

By Paul Scannell - 23 Mar, 2023 - Comments: 0

When I launched this blog series, I set out to share some of the more unique industry transitions I’ve witnessed over my 20+ year career in EDA. The B2B sales process has not been immune to change and transition. In fact, you could create a college curriculum with a daunting syllabus on the major transitions that have impacted the B2B sales process. I won’t drop that on you. The room wh... » read more

Managing EDA’s Rapid Growth Expectations

By Brian Bailey - 23 Mar, 2023 - Comments: 0

The EDA industry has been doing very well recently, but how long this run will continue is a matter of debate. EDA is an industry ripe for disruption due to rapid changes in chip architectures, end markets, and a long list of new technologies. In addition, recent geopolitical tensions are bringing a lot more attention to this small sector upon which the whole semiconductor industry rests. De... » read more

AI: Engineering Tool Or Threat To Jobs?

By Ed Sperling - 02 Mar, 2023 - Comments: 0

Semiconductor Engineering sat down to talk about using AI for designing and testing complex chips with Michael Jackson, corporate vice president for R&D at Cadence; Joel Sumner, vice president of semiconductor and electronics engineering at National Instruments; Grace Yu, product and engineering manager at Meta; David Pan, professor in the Department of Electrical and Computer Engineering a... » read more

Big Changes Ahead For Chip Technology And Industry Dynamics

By Ed Sperling - 08 Feb, 2023 - Comments: 0

Semiconductor Engineering sat down to discuss the impact of customization and advanced packaging, and concerns about reliability and geopolitical rivalries with Martin van den Brink, president and CTO of ASML; Luc Van den Hove, CEO of imec; David Fried, vice president of computational products at Lam Research; and Ankur Gupta, vice president and general manager of the test group and lifecycle s... » read more

What Does 2023 Have In Store For Chip Design?

By Brian Bailey - 26 Jan, 2023 - Comments: 0

Predictions seem to be easier to make during times of stability, but they are no more correct than at any other period. During more turbulent times, fewer people are courageous enough to allow their opinions to be heard. And yet it is often those views that are more well thought through, and even if they turn out not to be true, they often contain some very enlightening ideas. 2022 saw some ... » read more

EDA, IP Growth Surges Again

By Ed Sperling - 24 Jan, 2023 - Comments: 0

EDA tools and IP revenue increased 8.9% in Q3 of 2022 to $3.767 billion, up from $3.458 billion in 2021, according to a just-released report from the ESD Alliance at SEMI. All regions except Japan reported growth, but the numbers were a bit more uneven in Q3 than in recent quarters. For example, total silicon IP dropped 1%, while services revenue grew 20.8%. At the same time, EDA revenue jum... » read more

Selecting The Right RISC-V Core

By Brian Bailey - 16 Jan, 2023 - Comments: 0

With an increasing number of companies interested in devices based on the RISC-V ISA, and a growing number of cores, accelerators, and infrastructure components being made available, either commercially or in open-source form, end users face an increasingly difficult challenge of ensuring they make the best choices. Each user likely will have a set of needs and concerns that almost equals th... » read more

Variability Becoming More Problematic, More Diverse

By Karen Heyman - 12 Dec, 2022 - Comments: 0

Process variability is becoming more problematic as transistor density increases, both in planar chips and in heterogeneous advanced packages. On the basis of sheer numbers, there are many more things that can wrong. “If you have a chip with 50 billion transistors, then there are 50 places where a one-in-a-billion event can happen,” said Rob Aitken, a Synopsys fellow. And if Intel’s... » read more

Improving Concurrent Chip Design, Manufacturing, And Test Flows

By Ann Mutschler - 28 Nov, 2022 - Comments: 0

Semiconductor design, manufacturing, and test are becoming much more tightly integrated as the chip industry seeks to optimize designs using fewer engineers, setting the stage for greater efficiencies and potentially lower chip costs without just relying on economies of scale. The glue between these various processes is data, and the chip industry is working to weave together various steps t... » read more

An Organic Package Designer’s Guide To Transitioning To FOWLP And 2.5D Design

By Siemens EDA - 23 Nov, 2022 - Comments: 0

The IC packaging design tool set has matured to the point where it can address not only classic plastic, organic and ceramic packaging substrates but can also address silicon substrates driven by interposer and chiplet designs. In most cases system and packaging teams do not have to abandon their existing tool set to support these designs. In fact, the packaging design tool set can offer additi... » read more

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Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

Why Small Fab And Assembly Houses Are Thriving

Megafabs churning out the most advanced processors are not the only game in town.

by Bryon Moyer

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