tag: FD-SOI

Who’s Winning The FinFET Foundry Race?
By Mark LaPedus - 14 Aug, 2014 - Comments: 5

The leading-edge foundry business is challenging. For starters, foundry vendors require vast resources, gigantic fabs and lots of know-how. And yet, it’s still difficult to make money in this business. That has certainly proven to be the case in the planar transistor era, but the challenges and costs are escalating as foundry vendors begin to ramp up finFET technologies at the 16nm/14nm no... » read more

Power Reduction Techniques
By Mary Ann White - 07 Aug, 2014 - Comments: 0

As 16nm and 14nm finFET process nodes come into production toward the end of this year, the performance (up to 30% vs. 28nm planar CMOS), power (~30%) and area (up to ~50%) benefits have been well documented. The same can be said for the 28nm FD-SOI process as it gains more traction in the marketplace touting similar performance and power improvements as those for FinFET when compared against i... » read more

Reversing Course, With A Twist
By Brian Bailey - 24 Jul, 2014 - Comments: 1

Semiconductor Engineering is running an extended series of articles that examine the assertion that the end of Moore’s Law will have profound implications for the entire semiconductor, EDA and IP industries. Part one of this article, which focuses on the EDA industry, addressed the question about who was going to pay for future development of EDA tools for the latest production nodes. The ind... » read more

All Roads Point Up…But When?
By Ed Sperling - 17 Jul, 2014 - Comments: 0

One of the clear messages at Semicon West this month was that stacked die are coming soon. The only question is how soon. This isn’t so simple to answer. It depends on a lot of factors, and for most of them there aren’t any clear answers. First of all, no one is certain what the cost equation will look like at 14/16nm, particularly once the process technology becomes more mature. Ther... » read more

Confusion Does Not Equal Paralysis
By Ed Sperling - 10 Jul, 2014 - Comments: 0

After attending the two biggest semiconductor conferences in the world, along with a long list of notable conferences targeted to a wide variety of technologies and engineering disciplines, it’s clear the industry is racing ahead. But “ahead” is now a relative term. While Moore’s Law satisfied both economic and technological requirements, it was easy to figure out what “ahead” me... » read more

The Week In Review: Design
By Ed Sperling - 27 Jun, 2014 - Comments: 0

Tools eSilicon uncorked a GDSII online quote system for TSMC, which allows chipmakers to pick a variety of information ranging from process technology to package to yield and tapeout and production forecast and get a quote within minutes. This is a new twist in the value chain provider market. Synopsys added program to speed up FPGA-based prototype creation, which includes approved third-pa... » read more

Semiconductor R&D Crisis Ahead?
By Ed Sperling - 26 Jun, 2014 - Comments: 0

Listen to engineering management at chipmakers these days and a consistent theme emerges: They’re all petrified about where to place their next technology bets. Do they move to 14/16nm finFETs with plans to shrink to 10nm, 7nm and maybe even 5nm? Do they invest in 2.5D and 3D stacked die? Or do they eke more from existing process nodes using new process technologies, more compact designs and ... » read more

The Week In Review: Design
By Ed Sperling - 06 Jun, 2014 - Comments: 0

Tools Mentor Graphics rolled out embedded Linux software for AMD’s x86 G-series SoCs, code-named Steppe Eagle and its Crowned Eagle CPUs. Ansys-Apache and TowerJazz have created a power noise and reliability signoff design kit, including reference flow guidelines, test case examples and flow setup guidance. Synopsys updated its verification portfolio with static and formal tools for CD... » read more

The Week In Review: Design
By Ed Sperling - 16 May, 2014 - Comments: 0

M&A Synopsys’ Coverity subsidiary bought Kalistick, a French company that makes cloud-based solutions to boost testing efficiency by allowing engineers to identify and prioritize tests. Terms of the deal were not disclosed. Tools Cadence rolled out verification IP for the new PCI Express 4.0 architecture. The new spec supports up to 16 billion transactions per second, which is double... » read more

Drowning In Choices
By Ed Sperling - 15 May, 2014 - Comments: 0

There are at least half a dozen possible options for 28nm process technologies. There will be even more for the finFET generation. And that’s just the beginning of how complicated things will become over the next few years. There are multiple ways to test, seemingly infinite numbers of IP offerings—even from the same IP providers—and even more packaging options to put them together. Th... » read more

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