tag: IP

Executive Insight: Kathryn Kranen
By Ed Sperling - 17 Feb, 2014 - Comments: 0

Semiconductor Engineering sat down with Kathryn Kranen, president and CEO of Jasper Design Automation, to discuss what's changing in the semiconductor industry, why that's happening, and what to watch out for. The interview is part of an ongoing series of in-depth interviews with top executives from all segments of the industry. SE: What keeps you up at night? Kranen: Figuring out ways to... » read more

SoC Integration Mistakes
By Ed Sperling - 13 Feb, 2014 - Comments: 2

Semiconductor Engineering sat down to discuss integration challenges with Ruggero Castagnetti, distinguished engineer at LSI; Rob Aitken, an ARM fellow; Robert Lefferts, director of engineering in Synopsys’ Solutions Group; Bernard Murphy, chief technology officer at Atrenta; and Luigi Capodieci, R&D fellow at GlobalFoundries. What follows are excerpts of that roundtable discussion. SE... » read more

Cadence To Buy Forte
By The SE Staff - 05 Feb, 2014 - Comments: 2

Cadence agreed to buy Forte Design Systems for an undisclosed sum, enhancing its footprint in the high-level synthesis market as higher levels of abstraction gain traction across the SoC world. For the better part of a decade high-level synthesis (HLS) has been a market opportunity that was just around the next bend, along with electronic system-level design and SystemC modeling. Mentor Grap... » read more

The Next Big Threat: System Security
By Ed Sperling - 31 Jan, 2014 - Comments: 0

No SoC ever will be totally secure, and no technology will stop experienced thieves who really want to get into a device. But chipmakers and IP companies are examining ways to at least make it more difficult—and at least in theory, far less lucrative. One big change, of course, is that a connected electronic ecosystem has made location irrelevant. In the past, crime was limited to where th... » read more

Patents Under Scrutiny
By Brian Bailey - 30 Jan, 2014 - Comments: 2

After years of complaints by high-tech companies that the U.S. patent system is misused, too slow or completely outdated, patent attorneys are about to get their day in court. The U.S. Supreme Court has agreed to review an appeal between Alice Corp., an electronic marketplace for trading IP, and CLS Bank International, involving what kinds of inventions can be patented, according to the Supr... » read more

Experts At The Table: Yield And Reliability Issues With Integrating IP
By Ed Sperling - 27 Jan, 2014 - Comments: 1

Semiconductor Engineering sat down to discuss the impact of integrating IP in complex SoCs with Juan Rey, senior director of engineering at Mentor Graphics; Kevin Yee, product marketing director for Cadence’s SoC Realization Group; and Mike Gianfagna, vice president of marketing at eSilicon. What follows are excerpts of that conversation. SE: As an industry we’ve got a pretty good grasp ... » read more

Week In Review: System-Level Design
By Ed Sperling - 17 Jan, 2014 - Comments: 0

Cadence rolled out a new version of its functional verification platform, greatly improving performance and updating it to deal with the big increases in third-party and re-used IP in designs. For IP and block verification, the company said it increased formal analysis performance by up to 20% and simulation by up to 10 times. The debugger also reduces the database size by 10 times and the time... » read more

Which IP Is Better?
By Ed Sperling - 16 Jan, 2014 - Comments: 0

As the amount of third-party and re-used IP in a semiconductor increases, so do the number of questions about which possible IP choices perform better, use the least power, or work best with other components. So far, there is no simple way to make that choice. In most cases, this is simply splitting hairs. For all the IP that goes into designs, the bulk of it is chosen based on how often has... » read more

Reducing Power Consumption in Mobile Applications with High-Speed Gear3 MIPI M-PHY IP
By Various Writers - 15 Jan, 2014 - Comments: 1

Mobile systems require increasing data volume for multiple chip-to-chip interfaces. The high-speed MIPI® M-PHY is tailored for mobile systems where performance, power, and efficiency are key criteria. With up to 5,824 Mbps bandwidth, the speed meets devices’ high bandwidth and scalability requirements. The M-PHY is designed to accommodate the intermittent nature of inter-chip communications ... » read more

The Integrated IP Subsystem: A Converging SoC Solution
By Various Writers - 15 Jan, 2014 - Comments: 0

The consumer device market is witnessing incredible market space convergence between mobile handheld, automotive, and home electronics. IP vendors, engineers, and system design engineers face a multitude of challenges when designing and developing ICs, systems, or subsystems for the next great portable device. The next cell phone for instance, will not only be a multimedia player, but also a ... » read more

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