Will It Really Work?

By Ed Sperling - 26 Jan, 2012 - Comments: 0

By Ed Sperling Estimates of how much time it takes to verify a complex SoC are still hovering around 70% of the total non-recurring engineering costs, but with more unknowns and more things to verify it’s becoming harder to keep that number from growing. Verification has always been described as an unbounded problem. You can always verify more, and just knowing when to call it quits is so... » read more

Make Vs. Buy

By Ed Sperling - 17 Nov, 2011 - Comments: 0

By Ann Steffora Mutschler The confounding ‘make versus buy’ decision is understandably muddled by design complexity. Millions of gates, thousands of blocks, dozens of cores, plus software, packaging, and worries about physical effects don’t make this decision any easier. In some cases the process can be simplified by mandating that anything that doesn’t add differentiation really is... » read more

Managing IP In Complex Devices

By Ann Mutschler - 17 Nov, 2011 - Comments: 0

By Ann Steffora Mutschler Whether it is a smartphone, tablet, video game with home networking feature or any other digital device, each contains multiple subsystems with a mixture of IP blocks from either in-house development or licensed from third parties. Managing the subsystems, let alone the individual IP blocks and the interplay between all of them, is not getting any easier. In fact, wit... » read more

IP Tagging Resurfaces

By Ed Sperling - 30 Jun, 2011 - Comments: 0

By Ed Sperling System-Level Design sat down with Kathy Werner, IP strategy and business manager inside of Freescale’s Design Technology Organization, to discuss tagging of soft IP. What follows are excerpts of that conversation. SLD: How new is the concept of IP tagging? Werner: IP tagging has been around for a long time. VSI Alliance was one of the first standards organizations that l... » read more

What’s A Subsystem?

By Ed Sperling - 24 Jun, 2011 - Comments: 0

The interchangeability of IP has proved to be a myth. While large companies have been able to tap into their internally developed IP quite successfully, the ability to use commercially available IP has proved to be limited—particularly outside of the standard IP world. That will change, but not in the way most of the small IP companies actually expected. While the barrier to entry for deve... » read more

Effects Unknown

By Ed Sperling - 22 Apr, 2011 - Comments: 0

f you really want to know what’s going on inside the IC design world, pick up a copy of the annual reports of the largest foundries. Then triangulate that with the earnings reports of the largest makers of computers and mobile electronics and the makers of EDA tools and IP. All three areas are experiencing a massive uptick, which is good news considering the travails of the past couple of ... » read more

The Quest For A Better IP Integration Methodology

By Ed Sperling - 31 Mar, 2011 - Comments: 0

By Ed Sperling With the amount of IP in SoC designs now hitting an estimated 70% to 90%, companies are scrambling to figure out a way to more consistently integrate that IP and to test that it will work as expected. This is easier said than done, however, for a number of reasons: There are numerous types of IP, ranging from I/O to logic and memory. Not all IP is of equal quality. ... » read more

Engineering’s Growing Blacklist

By Ed Sperling - 25 Mar, 2011 - Comments: 0

The number of system-level design flaws is rising, and they’re not just little mistakes. These are high-profile errors that are making headlines all over the globe. While it’s debatable whether Toyota’s problem was a hardware or software design glitch, the simple fact is there was a design flaw somewhere. That’s true for the BP Gulf of Mexico leak, regardless of who’s responsible f... » read more

The Growing Importance Of Subsystems

By Ed Sperling - 24 Feb, 2011 - Comments: 0

By Ed Sperling A growing reliance on third-party IP is beginning to expand well beyond just IP blocks and into full subsystems, opening significant growth opportunities for companies competing in this market as well as enormous business and technical challenges. The IP market is ripe for this kind of convergence. Complexity at advanced process nodes coupled with time-to-market demands has e... » read more

Tailoring IP, Tools And Flows

By Ed Sperling - 27 Jan, 2011 - Comments: 0

By Ann Steffora Mutschler As SoC and system complexity rises continually and software drives much more in a system, specific vertical application areas will require tailored IP and tool flows to allow designers to meet time-to-market demands. Today, many systems are designed around a platform, which contains most of the STAR IP—processors, GPUs, memory controllers, interconnects, memory s... » read more

← Older posts Newer posts →

Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

tag: IP