tag: mixed signal

Extending The Benefits Of UVM To Include AMS: An Update On Accellera’s UVM-AMS Standard Development
By Tom Fitzpatrick - 04 Oct, 2022 - Comments: 0

By Tom Fitzpatrick and Peter Grove SoC teams can be divided up into design and verification groups. For digital designs, the Universal Verification Methodology (UVM), initially developed by Accellera and now standardized as IEEE 1800.2, has been the industry standard for the past decade. Since most SoC designs also have analog and mixed-signal IP blocks, it would be ideal for verification en... » read more

Improving Design Collaboration In The Age Of Remote Work
By Amit Varde - 13 Sep, 2022 - Comments: 0

Teams of analog and mixed signal (AMS) design and layout engineers spend countless hours extracting every ounce of performance out of their design. They continually make incremental changes daily to the design until the very end, as close to tape out as possible. Each change made to the design requires corresponding changes to the circuit layout. As technology advances, accounting for the paras... » read more

Algorithm HW Framework That Minimizes Accuracy Degradation, Data Movement, And Energy Consumption Of DNN Accelerators (Georgia Tech)
By Technical Paper Link - 31 Aug, 2022 - Comments: 0

This new research paper titled "An Algorithm-Hardware Co-design Framework to Overcome Imperfections of Mixed-signal DNN Accelerators" was published by researchers at Georgia Tech. According to the paper's abstract, "In recent years, processing in memory (PIM) based mixed-signal designs have been proposed as energy- and area-efficient solutions with ultra high throughput to accelerate DNN com... » read more

Auto Chipmakers Dig Down To 10ppb
By Anne Meixner - 08 Mar, 2022 - Comments: 0

How do engineers deliver 10 defective parts per billion (Dppb) to auto makers if they only screen 1 million parts per year? Answer: By comprehending failure mechanisms and proactively screening for them. Modern automobiles contain nearly 1,000 ICs that must perform over the vehicle’s life (15 years). This drives quality expectations ever higher. While 10 Dppm used to be a solid benchmark, ... » read more

Holistic FMEDA-Driven Safety Design And Verification For Analog, Digital, And Mixed-Signal Design
By Cadence - 21 Dec, 2021 - Comments: 0

With state-of-the-art electronics propelling the automotive industry into the future, automotive OEMs require safety-certified semiconductors. The integration of these advanced technologies into cars drives a need for component suppliers to assess and audit the risk of the technologies they want to deploy. At the same time, safety requirements are constantly evolving and becoming more stringent... » read more

Anti-Tamper Benefits Of Encrypted Helper-Data Images For PUFs
By Rambus - 01 Dec, 2021 - Comments: 0

PUFs are mixed-signal circuits which rely on variations unique to a specific chip to self-generate a digital “fingerprint.” Most PUFs require a “helper-data” image that is generated during the initial digitization process, also known as Enrollment. Leveraging the chip-unique transformation function of PUFs and encrypted helper data, an unclonable challenge-response mechanism can be impl... » read more

‘Hug The Debug’ – Before It’s Too Late
By Sumit Vishwakarma - 01 Jul, 2021 - Comments: 0

Though the term “shift-left” originated in the software industry, its importance is often cited in the hardware (semiconductor) industry where the end-product (chip) costs are skyrocketing. The increase in cost is driven by a global chip shortage, especially in the automotive industry. Manufacturing a robust chip is a long, iterative process that may require many re-spins. Shift-left refers... » read more

Virtuoso ADE Assembler
By Cadence - 26 May, 2021 - Comments: 0

Cadence Virtuoso ADE Assembler is an advanced design and simulation environment that extends the capabilities of Virtuoso ADE Explorer, adding all the tests needed to fully verify a design over all operational, process, and environmental conditions. As more analysis is required, users can take incremental advantage of the Virtuoso Variation Option to do more advanced statistical analysis on the... » read more

Testing Analog Circuits Becoming More Difficult
By Susan Rambo - 11 May, 2021 - Comments: 1

Foundries and packaging houses are wrestling how to control heat in the testing phase, particularly as devices continue to shrink and as thermally sensitive analog circuits are added into SoCs and advanced packages to support everything from RF to AI. The overriding problem is that heat can damage chips or devices under test. That's certainly true for digital chips developed at advanced node... » read more

Re-Architecting SerDes
By Brian Bailey - 10 Dec, 2020 - Comments: 0

Serializer/Deserializer (SerDes) circuits have been helping semiconductors move data around for years, but new process technologies are forcing it to adapt and change in unexpected ways. Traditionally implemented as an analog circuit, SerDes technology has been difficult to scale, while low voltages, variation, and noise are making it more difficult to yield sufficiently. So to remain releva... » read more

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