The Week In Review: Manufacturing

By Mark LaPedus - 10 Apr, 2015 - Comments: 1

Intel is quietly delaying its process ramp at the 10nm node, according to multiple sources. In an e-mail, a spokesman for Intel said: “We have not disclosed a schedule for our 10nm process and we won't engage in speculation about it.” In March, though, Intel was supposed to make fab tool buys for high-volume manufacturing at 10nm, sources said. But now, those purchases won’t happen... » read more

Stacked Die, Phase Two

By Ed Sperling - 09 Apr, 2015 - Comments: 0

The initial hype phase of [getkc id="82" kc_name="2.5D"] appears to be over. There are multiple offerings in development or on the market already from Xilinx, Altera, Cisco, Huawei, IBM, AMD, all focused on better throughput over shorter distances with better yield and lower power. Even Intel has jumped on the bandwagon, saying that 2.5D will be essential for extending [getkc id="74" comment="M... » read more

One-On-One: Dark Silicon

By Katherine Derbyshire - 09 Apr, 2015 - Comments: 0

Professor Michael Taylor’s research group at UC San Diego is studying ways to exploit dark silicon to optimize circuit designs for energy efficiency. He spoke with Semiconductor Engineering about the post-Dennard scaling regime, energy efficiency from integrated circuits all the way up to data centers, and how the manufacturing side can help. What follows are excerpts of that conversation. (F... » read more

How We’ll Get There from Here

By Brian Fuller - 09 Apr, 2015 - Comments: 0

The electronics industry is like a battleship with remarkable handling properties. I thought about it this week sitting at an industry event a day after stumbling across Neptune—the technology project, not the god. Those two experiences forced me to rethink some fundamental assumptions about system design and how the ecosystem responds to change. If you’ve not heard of Neptune, it�... » read more

Blog Review: April 8

By Jesse Allen - 08 Apr, 2015 - Comments: 0

No other human endeavor has seen such sustained exponential growth. But it's the end of an era for Moore's Law, says Cadence's Axel Scherer—and only the beginning of one for Moore's Law 2.0. Synopsys' Amit Sharma tackles the cache coherency extensions of the ARM Advanced eXtensible Interface (AXI) and points out that the infrastructure required for their verification needs to scale up in s... » read more

Ecosystem Changes

By Ed Sperling - 07 Apr, 2015 - Comments: 0

Semiconductor Engineering sat down to discuss changes in the semiconductor ecosystem with Kelvin Low, senior director of foundry marketing at [getentity id="22865" e_name="Samsung Semiconductor"]; John Costello, vice president of product planning at [getentity id="22849" e_name="Altera"]; Randy Smith, vice president of marketing at [getentity id="22605" e_name="Sonics"], and Michiel Ligthart, p... » read more

Challenges Mount For Patterning And Masks

By Mark LaPedus - 06 Apr, 2015 - Comments: 0

Semiconductor Engineering sat down to discuss [getkc id="80" comment="lithography"] and photomask trends with Uday Mitra, vice president and chief technology officer for the Etch Business Unit at [getentity id="22817" e_name="Applied Materials"]; Pawitter Mangat, senior manager and deputy director for EUV lithography at [getentity id="22819" comment="GlobalFoundries"]; Aki Fujimura, chief execu... » read more

Challenges Mount For Patterning And Masks

By Mark LaPedus - 30 Mar, 2015 - Comments: 0

Semiconductor Engineering sat down to discuss lithography and photomask trends with Uday Mitra, vice president and chief technology officer for the Etch Business Unit at [getentity id="22817" e_name="Applied Materials"]; Pawitter Mangat, senior manager and deputy director for EUV lithography at [getentity id="22819" comment="GlobalFoundries"]; Aki Fujimura, chief executive at [getentity id="228... » read more

Week 42: Celebrating The 50th Anniversary Of Moore’s Law At DAC

By Anne Cirkel - 27 Mar, 2015 - Comments: 0

April 19th will mark the 50th anniversary of Gordon Moore’s now famous paper in Electronics Magazine predicting that the number of transistors on a chip will double every year. In 1975, Moore—Intel’s co-founder—revised the period to every two years, and it is still holding true. Moore’s Law not only became a legendary prediction and long-term planning guide for the semiconductor indus... » read more

Challenges Mount For Patterning And Masks

By Mark LaPedus - 19 Mar, 2015 - Comments: 0

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Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

Legacy Process Nodes Going Strong

The critical, and growing, significance of mature node chips and processes.

by Bryon Moyer

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

tag: Moore’s Law

The Week In Review: Manufacturing

Stacked Die, Phase Two

One-On-One: Dark Silicon

How We’ll Get There from Here

Blog Review: April 8

Ecosystem Changes

Challenges Mount For Patterning And Masks

Challenges Mount For Patterning And Masks

Week 42: Celebrating The 50th Anniversary Of Moore’s Law At DAC

Challenges Mount For Patterning And Masks