tag: SoC

Realizing the Benefits of 14/16nm Technologies
By eSilicon - 31 Jan, 2019 - Comments: 0

The scaling benefits of Moore’s Law are challenging below 28nm. It is no longer a given that the cost per gate will go down at process nodes below 28nm, e.g., 20nm though 14nm and 7nm. Rising design and manufacturing costs are contributing factors to this trend. Meanwhile, the competing trend of fewer but more complex system-on-chip (SoC) designs is reducing the knowledge base of many chip... » read more

EDA Grabs Bigger Slice Of Chip Market
By Brian Bailey - 31 Jan, 2019 - Comments: 0

EDA revenues have been a fairly constant percentage of semiconductor revenues, but that may change in 2019. With new customers creating demand, and some traditional customers shifting focus from advanced nodes, the various branches of the EDA tool industry may be where sticky technical problems are solved. IC manufacturing, packaging and development tools all are finding new ways to handle t... » read more

Week in Review: IoT, Security, Auto
By Jeff Dorsch - 25 Jan, 2019 - Comments: 0

Internet of Things Tony Franklin, Intel’s general manager for Internet of Things Segments, is interviewed by Lorin Fries on how the chipmaker is helping to develop smart farming applications. “We focus primarily on high-performance computer technologies, as well as communication technologies, which have great applicability for food systems. We work closely with a broad ecosystem of partner... » read more

Concurrent Test
By Ed Sperling - 11 Jan, 2019 - Comments: 0

Derek Wu, senior staff applications engineer at Advantest, looks at the need for doing multiple tests at the same time as chip designs become more complex, increasingly heterogeneous, and much more difficult to test at advanced nodes. https://youtu.be/-8inbjX_af0       __________________________________ See more tech talk videos here. » read more

Debug Tops Verification Tasks
By Ann Mutschler - 20 Dec, 2018 - Comments: 0

Verification engineers are spending an increased percentage of their time in debug — 44%, according to a recent survey by the Wilson Research Group. There are a variety or reasons for this, including the fact that some SoCs are composed of hundreds of internally developed and externally purchased IP blocks and subsystems. New system architectures contribute to the mix, some of which are be... » read more

AI Market Ramps Everywhere
By Brian Bailey - 20 Dec, 2018 - Comments: 0

Artificial Intelligence (AI) has inspired the general populace, but its rapid rise over the past few years has given many people pause. From realistic concerns about robots taking over jobs to sci-fi scares about robots more intelligent than humans building ever smarter robots themselves, AI inspires plenty of angst. Within the technology industry, we have a better understanding about the pote... » read more

Quantifying the Value of On-Chip Debug
By UltraSoC - 19 Dec, 2018 - Comments: 0

White paper authored by Semico Research, quantifies the benefits of using on-chip debug and monitoring technology, specifically UltraSoc's technology. Rising design complexityIn the last several years, contemporary SoCs (system-on-a-chip) have become increasingly complex. They now consist of 100s of millions of gates, 100 or more discrete semiconductor intellectual property (SIP) blocks, hi... » read more

How to Make Sure IP will Float in the Rough SoC Sea
By Magdy Abadir - 19 Dec, 2018 - Comments: 0

Today a typical SoC includes hundreds of instances of IP modules both digital and analog. These IPs are typically verified individually by the vendors. The burden of guaranteeing functionality when placed in the midst of a monster SoC is typically left to the SoC owner. With increasing frequencies, tighter margins, denser integrated circuits, new devices and materials, the task of verifying So... » read more

The DNA of an Artificial Intelligence SoC
By Synopsys - 19 Dec, 2018 - Comments: 0

Over the past decade, a few advancements have made artificial intelligence (AI) one of the most exciting technologies of our lifetime. In 2012, Geoffrey Everest Hinton demonstrated his generalized back propagation neural network algorithm in the Imagenet challenge, which revolutionized the field of computer vision. However, the math was developed years prior to 2012, and it was the available m... » read more

Softening Hardware: Using Application-Specific Processors to Optimize Modern SoC Designs
By Synopsys - 12 Dec, 2018 - Comments: 0

Over the past decade, the trend in SoC design has been to add more functionality into software, but moving functionality from hardware into software comes at a cost: software requires a processor, which, if not designed for optimal efficiency, could be slower and use more power than dedicated hardware. It often makes sense to implement smaller, specialized processors to tackle specific tasks wi... » read more

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