tag: test

Auto Chip Test Issues Grow
By Jeff Dorsch - 08 Jan, 2018 - Comments: 0

By Jeff Dorsch & Ed Sperling Semiconductor suppliers are flocking to the automotive chip market to gain share in fitting out the connected car and the autonomous vehicle. But before those chips are sold to automotive manufacturers and Tier 1 suppliers, they must be tested and certified to meet stringent industry standards. This is no ordinary testing, though. Assisted and autonomous v... » read more

Getting Serious About Chiplets
By Ann Mutschler - 08 Jan, 2018 - Comments: 0

Demand for increasingly complex computation, more features, lower power, and shorter lifecycles are prompting chipmakers to examine how standardized hard IP can be used to quickly assemble systems for specific applications. The idea of using chiplets, with or without a package, has been circulating for at least a half-dozen years, and they can trace their origin back to IBM's packaging schem... » read more

Changes Ahead For Test
By Jeff Dorsch - 11 Dec, 2017 - Comments: 0

Testing microprocessors is becoming more difficult and more time consuming as these devices are designed to take on more complex tasks, such as accelerating artificial intelligence computing, enabling automated driving, and supporting deep neural networks. This is not just limited to microprocessors, either. Graphics processing units are grabbing market share in supercomputing and other area... » read more

Securing Your Test System
By NI - 11 Dec, 2017 - Comments: 0

Test systems, like other industrial equipment, are vulnerable to cyber attacks. That requires a phased approach to cyber security, addressing the most likely threats first and communicating with suppliers to understand threats upstream in the supply chain. To read more, click here. » read more

How To Sleep Easier If You Test Auto ICs For A Living
By Andrew Macleod - 07 Dec, 2017 - Comments: 0

Last month, I looked at the product definition process of automotive ICs, using the $7 billion microcontroller market as an illustration of design exploration to optimize performance, features, die size and product cost. Now I’d like to look at the back end of the process — the final IC testing that’s still critical no matter how sound the upfront work in defining a featuring set and aptl... » read more

Tech Talk: Near-Threshold Power
By Ed Sperling - 13 Nov, 2017 - Comments: 2

Lauri Koskinen, CTO and founder of Minima Processor, and Ron Moore, vice president of marketing at ARM, talk about near-threshold computing, dynamic power and margining, and how these techniques can extend battery life and reduce energy consumption. https://youtu.be/BhiNFe4NYQU » read more

Lots Of Little Knobs For Power
By Ann Mutschler - 09 Nov, 2017 - Comments: 3

Dynamic power is becoming a much bigger worry at new nodes as more finFETs are packed on a die and wires shrink to the point where resistance and capacitance become first-order effects. Chipmakers began seeing dynamic power density issues with the first generation of [getkc id="185" kc_name="finFETs"]. While the 3D transistor structures reduced leakage current by providing better gate contro... » read more

What’s Missing In Packaging
By Ed Sperling - 06 Nov, 2017 - Comments: 0

The growth of advanced packaging on the leading edge of design is inching backwards into older nodes. With most technology—tools, methodologies, materials and processes—this is business as usual. But in packaging, it's both counterintuitive and potentially problematic. The main reason that companies began investing in advanced packaging—OSATs, foundries, chipmakers such as Intel and Qu... » read more

2017 ITC Wrap-up
By Jeff Dorsch - 06 Nov, 2017 - Comments: 0

Advantest was among the exhibitors and corporate sponsors at last week’s 2017 International Test Conference in Fort Worth, Texas. The automatic test equipment company also presented papers, took part in sessions, and provided posters during ITC’s technical program. In the booth, Advantest demonstrated its on-demand CloudTesting Service. It also showed off its EVA100 analog/mixed-signal IC t... » read more

STMicroelectronics’ Implementation Of The STAR Hierarchical System And IEEE 1500 Wrapping
By Synopsys - 01 Nov, 2017 - Comments: 0

This white paper discusses various IEEE 1500 architectures that STMicroelectronics has deployed using the Synopsys DesignWare STAR Hierarchical System test solution. STAR Hierarchical System allows users to optimize test time on system-on-chips that use multiple cores. The white paper provides guidelines on interface IP wrapping with IEEE 1500 to improve test time. In addition, it discusses the... » read more

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