The Good And Bad Of Chiplets

By Mark LaPedus - 27 May, 2020 - Comments: 1

The chiplet model continues to gain traction in the market, but there are still some challenges to enable broader support for the technology. AMD, Intel, TSMC, Marvell and a few others have developed or demonstrated devices using chiplets, which is an alternative way to develop an advanced design. Beyond that, however, the adoption of chiplets is limited in the industry due to ecosystem issu... » read more

Rising Packaging Complexity

By Ed Sperling - 19 May, 2020 - Comments: 1

Synopsys’ Rita Horner looks at the design side of advanced packaging, including how tools are chosen today, what considerations are needed for integrating IP while maintaining low latency and low power, why this is more complex in some ways than even the most advanced planar chip designs, and what’s still missing from the tool flow. » read more

The Need For 3D IC Packaging And Design Evolution

By Rita Horner - 14 May, 2020 - Comments: 0

If you are familiar with Moore’s Law, you’ve probably read pronouncements that the premise of transistor counts doubling each year is reaching a wall due to complex process technologies and device physics limitations. Regardless of how well transistor counts continue to scale, market segments continue to drive the thirst for more compute performance and fast time to markets. Artificial i... » read more

‘More Than Moore’ Reality Check

By Ann Mutschler - 14 May, 2020 - Comments: 1

The semiconductor industry is embracing multi-die packages as feature scaling hits the limits of physics, but how to get there with the least amount of pain and at the lowest cost is a work in progress. Gaps remain in tooling and methodologies, interconnect standards are still being developed, and there are so many implementations of packaging that the number of choices is often overwhelming. ... » read more

New Uses For Manufacturing Data

By Ed Sperling - 12 May, 2020 - Comments: 0

The semiconductor industry is becoming more reliant on data analytics to ensure that a chip will work as expected over its projected lifetime, but that data is frequently inconsistent or incomplete, and some of the most useful data is being hoarded by companies for competitive reasons. The volume of data is rising at each new process node, where there are simply more things to keep track of,... » read more

An Inside Look At Testing’s Leading Edge

By Ed Sperling - 12 May, 2020 - Comments: 0

Mike Slessor, president and CEO of FormFactor, sat down with Semiconductor Engineering to discuss testing of AI and 5G chips, and why getting power into a chip for testing is becoming more difficult at each new node. SE: How does test change with AI chips, where you've got massive numbers of accelerators and processors developed at 7 and 5nm? Slessor: A lot of the AI stuff that we've been... » read more

Reliability Monitoring Of GUC 7nm High-Bandwidth Memory (HBM) Subsystem

By proteanTecs - 27 Apr, 2020 - Comments: 0

This white paper presents the use of proteanTecs’ Proteus for HBM subsystem reliability based on deep data analytics and enhanced visibility, overcoming the limitations of advanced heterogeneous packaging. It will describe the operation concept and provide results from a GUC 7nm HBM Controller ASIC. A typical CoWoS chip has hundreds of thousands of micro-bumps (u-bumps). 3-8 u-bumps are us... » read more

A Node Too Far?

By Ed Sperling - 23 Apr, 2020 - Comments: 1

Physics is an unforgiving master. While the semiconductor industry has been actively developing new transistor structures, new materials for interconnects and lining trenches, and new approaches to alleviate congestion at the lowest metal levels, it also has been playing an accelerating game of Whac-a-Mole. Whenever a problem pops up, the solution to that problem is never complete and more prob... » read more

Using Big Data For Yield And Reliability

By Ed Sperling - 22 Apr, 2020 - Comments: 0

John O’Donnell, CEO of yieldHUB, talks about the importance of clean data for traceability, yield improvement and device reliability, where and how it gets cleaned, and why that needs to be accompanied by domain expertise. » read more

Making Chips At 3nm And Beyond

By Mark LaPedus and Ed Sperling - 16 Apr, 2020 - Comments: 4

Select foundries are beginning to ramp up their new 5nm processes with 3nm in R&D. The big question is what comes after that. Work is well underway for the 2nm node and beyond, but there are numerous challenges as well as some uncertainty on the horizon. There already are signs that the foundries have pushed out their 3nm production schedules by a few months due to various technical issu... » read more

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tag: advanced packaging

The Good And Bad Of Chiplets

Rising Packaging Complexity

The Need For 3D IC Packaging And Design Evolution

‘More Than Moore’ Reality Check

New Uses For Manufacturing Data

An Inside Look At Testing’s Leading Edge

Reliability Monitoring Of GUC 7nm High-Bandwidth Memory (HBM) Subsystem

A Node Too Far?

Using Big Data For Yield And Reliability

Making Chips At 3nm And Beyond

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