tag: advanced packaging

Variation Threat In Advanced Nodes, Packages Grows
By Ed Sperling - 21 Dec, 2020 - Comments: 0

Variation is becoming a much bigger and more complex problem for chipmakers as they push to the next process nodes or into increasingly dense advanced packages, raising concerns about the functionality and reliability of individual devices, and even entire systems. In the past, almost all concerns about variation focused on the manufacturing process. What printed on a piece of silicon didn't... » read more

The Darker Side Of Hybrid Bonding
By Katherine Derbyshire - 17 Dec, 2020 - Comments: 2

With semiconductors, it's often things everyone takes for granted that cause the biggest headaches, and that problem is compounded when something fundamental changes — such as bonding two chips together using a process aimed at maximizing performance. Case in point: CMP for backend of the line metallization in hybrid bonding. While this is a mature process, it doesn't easily translate for ... » read more

A Production-Worthy Fan-Out Solution — ASE FOCoS Chip Last
By ASE - 16 Dec, 2020 - Comments: 0

The 5th Generation (5G) wireless systems popularity will push the package development into a high performance and heterogeneous integration form. For high I/O density and high performance packages, the promising Fan Out Chip on Substrate (FOCoS) provides a solution to match outsourced semiconductor assembly and testing (OSAT) capability. FOCoS is identified the Fan Out (FO) package, which can f... » read more

Re-Architecting SerDes
By Brian Bailey - 10 Dec, 2020 - Comments: 0

Serializer/Deserializer (SerDes) circuits have been helping semiconductors move data around for years, but new process technologies are forcing it to adapt and change in unexpected ways. Traditionally implemented as an analog circuit, SerDes technology has been difficult to scale, while low voltages, variation, and noise are making it more difficult to yield sufficiently. So to remain releva... » read more

New Security Approaches, New Threats
By Ed Sperling - 09 Dec, 2020 - Comments: 0

New and different approaches to security are gaining a foothold as the life expectancy for advanced chips increases, and as emerging technologies such as quantum computing threaten to crack even the most complex encryption schemes. These approaches include everything from homomorphic encryption, where data is processed without being decrypted, to different ways of sending and receiving data ... » read more

Predicting Reliability At 3/2nm And Beyond
By Ed Sperling - 08 Dec, 2020 - Comments: 0

The chip industry is determined to manufacture semiconductors at 3/2nm — and maybe even beyond — but it's unlikely those chips will be the complex all-in-one SoCs that have defined advanced electronics over the past decade or so. Instead, they likely will be one of many tiles in a system that define different functions, the most important of which are highly specialized for a particular app... » read more

Adaptive Shot Technology To Address Severe Lithography Challenges For Advanced FOPLP
By Onto Innovation - 07 Dec, 2020 - Comments: 0

Fan-out wafer level packaging (FOWLP) is a popular new packaging technology that allows the user to increase I/O in a smaller IC size than fan-in wafer level packaging. Market drivers such as 5G, IoT, mobile and AI will all use this technology. According to Yole Développement’s analysis, the fan-out packaging market size will increase to $3 billion in 2022 from $2.44 hundred million in 2014,... » read more

What Interested You In 2020
By Brian Bailey - 24 Nov, 2020 - Comments: 0

In business you are always told to follow the money, but for us it is more important to follow the readership. If we are not writing what you want to read, then we are missing the mark. I like to review the ones that have garnered the most attention, in part to see if that will influence what I write about for 2021, but also to find out where the industry is looking for the most help. As Sem... » read more

Structural Integrity Of Chips
By Ed Sperling - 23 Nov, 2020 - Comments: 0

A new challenge is on the horizon, and it's one that could have some interesting consequences for chip design — structural integrity. Ever since the introduction of finFETs and 3D NAND, the lines have been blurring between electrical and mechanical engineering. After some initial reports of fins collapsing or breaking, and variable distances between layers, chipmakers figured out how to so... » read more

The Ten Commandments Of Packaging
By Sam Sadri - 19 Nov, 2020 - Comments: 0

Semiconductor packaging continues to evolve as chipmakers find new ways to fit more functionality into smaller spaces. Whereas the package once served primarily as a means of attaching a chip to a circuit board and protecting it from damage due to heat, moisture, etc., packaging today plays an important role in adding value to the device, boosting customization while helping to reduce costs. ... » read more

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