Packaging And Package Design For AI At The Edge


Industrial applications will acquire significantly more data directly from machines in coming years. To properly handle this increase in data, it must already be prepared at the machine. The data of the individual sensors can be processed, or an initial data merger can take place here at the so-called “edge.” Algorithms and methods from the field of artificial intelligence increasingly a... » read more

Test Costs Spiking


The cost of test is rising as a percentage of manufacturing costs, fueled by concerns about reliability of advanced-node designs in cars and data centers, as well as extended lifetimes for chips in those and other markets. For decades, test was limited to a flat 2% of total manufacturing cost, a formula developed prior to the turn of the Millennium after chipmakers and foundries saw the traj... » read more

Grading Chips For Longer Lifetimes


Figuring out how to grade chips is becoming much more difficult as these chips are used in applications where they are supposed to last for decades rather than just a couple of years. During manufacturing, semiconductors typically are run through a battery of tests involving performance and power, and then priced accordingly. But that is no longer a straightforward process for several reason... » read more

3nm: Blurring Lines Between SoCs, PCBs And Packages


Leading-edge chipmakers, foundries and EDA companies are pushing into 3nm and beyond, and they are encountering a long list of challenges that raise questions about whether the entire system needs to be shrunk onto a chip or into a package. For 7nm and 5nm, the problems are well understood. In fact, 5nm appears to be more of an evolution from 7nm than a major shift in direction. But at 3nm, ... » read more

Chip Design Is Getting Squishy


So many variables, uncertainties and new approaches are in play today across the chip industry today that previous rules are looking rather dated. In the past, a handful of large companies or organizations set the rules for the industry and established an industry roadmap. No such roadmap exists today. And while there are efforts underway to create new roadmaps for different industries, inte... » read more

Chiplet Momentum Rising


The chiplet model is gaining momentum as an alternative to developing monolithic ASIC designs, which are becoming more complex and expensive at each node. Several companies and industry groups are rallying around the chiplet model, including AMD, Intel and TSMC. In addition, there is a new U.S. Department of Defense (DoD) initiative. The goal is to speed up time to market and reduce the cost... » read more

Moore And More


For more than 50 years, the semiconductor industry has enjoyed the benefits of Moore's Law — or so it seemed. In reality, there were three laws rolled up into one: Each process generation would have a higher clock speed at the same power. This was not discovered by Moore, but by Dennard, who also invented the DRAM. Process generations continue to get faster and lower power, but the power... » read more

The MCU Dilemma


The humble microcontroller is getting squeezed on all sides. While most of the semiconductor industry has been able to take advantage of Moore's Law, the MCU market has faltered because flash memory does not scale beyond 40nm. At the same time, new capabilities such as voice activation and richer sensor networks are requiring inference engines to be integrated for some markets. In others, re... » read more

Is This The Year Of The Chiplet?


Customizing chips by choosing pre-characterized — and most likely hardened IP — from a menu of options appears to be gaining ground. It's rare to go to a conference these days without hearing chiplets being mentioned. At a time when end markets are splintering and more designs are unique, chiplets are viewed as a way to rapidly build a device using exactly what is required for a particul... » read more

5/3nm Wars Begin


Several foundries are ramping up their new 5nm processes in the market, but now customers must decide whether to design their next chips around the current transistor type or move to a different one at 3nm and beyond. The decision involves the move to extend today’s finFETs to 3nm, or to implement a new technology called gate-all-around FETs (GAA FETs) at 3nm or 2nm. An evolutionary step f... » read more

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