tag: aging

Monitoring Chips After Manufacturing
By Brian Bailey - 19 Aug, 2020 - Comments: 2

New regulations and variability of advanced process nodes are forcing chip designers to insert additional capabilities in silicon to help with comprehension, debug, analytics, safety, security, and design optimization. The impact of this will be far-reaching as the industry discusses what capabilities can be shared between these divergent tasks, the amount of silicon area to dedicate to it, ... » read more

Spreading Out The Cost At 3nm
By Ed Sperling - 18 Jun, 2020 - Comments: 5

The current model for semiconductor scaling doesn't add up. While it's possible that markets will consolidate around a few basic designs, the likelihood is that no single SoC will sell in enough volume to compensate for the increased cost of design, equipment, mask sets and significantly more testing and inspection. In fact, even with slew of derivative chips, it may not be enough to tip the ec... » read more

Aging Problems At 5nm And Below
By Brian Bailey - 11 Jun, 2020 - Comments: 3

The mechanisms that cause aging in semiconductors have been known for a long time, but the concept did not concern most people because the expected lifetime of parts was far longer than their intended deployment in the field. In a short period of time, all of that has changed. As device geometries have become smaller, the issue has become more significant. At 5nm, it becomes an essential par... » read more

Monitoring For In-Die Process Speed Detection
By Richard McPartland - 14 May, 2020 - Comments: 0

Chip designers working on advanced nodes typically include a fabric of sensors spread across the die for a number of very specific reasons. In this, the second of a three-part blog series, we explore some of the key applications and benefits of these types of sensing solutions. In this installment, the focus is In-Die Process Speed Detection and why understanding in-chip process speed detecti... » read more

Last-Level Cache
By Ed Sperling - 06 Apr, 2020 - Comments: 0

Kurt Shuler, vice president of marketing at Arteris IP, explains how to reduce latency and improve performance with last-level cache in order to avoid sending large amounts of data to external memory, and how to ensure quality of service on a chip by taking into account contention for resources. » read more

Aging Analysis Standard Solidifies Through Collaborative Effort
By Ahmed Ramadan - 12 Mar, 2020 - Comments: 0

By Ahmed Ramadan, Greg Curtis, Harrison Lee, Jongwook Kye, and Sorin Dobre We live in a connected world and it is estimated that by 20251 the total amount of worldwide data will swell to 163 ZB, or 163 trillion gigabytes. This rapid growth in data expansion is driving an explosion in new designs and new requirements for consumer, data center, automotive, and Internet of Things (IoT) applicat... » read more

Degradation Monitoring
By proteanTecs - 09 Mar, 2020 - Comments: 0

This paper describes a reliability degradation modeling and monitoring method based on a combination of IC novel embedded circuits (Agents), and off-chip machine learning algorithms which infer the digital readouts of these circuits during test and operational lifetime. Together, they monitor the margin degradation of an IC, as well as other vital parameters of the IC and its environmental s... » read more

Making Light More Reliable
By Ed Sperling - 11 Feb, 2020 - Comments: 0

The buzz around photonics in packages and between packages is growing. Now the question is whether it will work as expected, and where it will be useful. Replacing electrical with optical signals has been on the technology horizon for some time. Light moves faster through fiber than electrons through copper. How much faster depends upon the diameter of the wires, the substrate and interconne... » read more

Making 3D Structures And Packages More Reliable
By Ed Sperling - 14 Jan, 2020 - Comments: 0

The move to smaller vertical structures and complex packaging schemes is straining existing testing approaches, particularly in heterogeneous combinations on a single chip and in multi-die packages. The complexity of these devices has exploded with the slowdown in scaling, as chipmakers turn to architectural solutions and new transistor structures rather than just relying on shrinking featur... » read more

3 Safety Standards For Auto Electronics
By Ed Sperling - 13 Jan, 2020 - Comments: 0

Kurt Shuler, vice president of marketing at Arteris IP, drills down into the three main safety standards, ISO 26262, SOTIF (Safety of the Intended Function) and UL 4600, what each one covers, what the intent is behind them, and what this means for companies developing technology for future vehicles. » read more

← Older posts Newer posts →

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2024 SMG   |  Terms of Service  |  Privacy Policy