tag: ALD

Moving To GAA FETs
By Katherine Derbyshire - 20 Feb, 2020 - Comments: 2

How do you measure the size of a transistor? Is it the gate length, or the distance between the source and drain contacts? For planar transistors, the two values are approximately the same. The gate, plus a dielectric spacer, fits between the source and drain contacts. The contact pitch, limited by the smallest features that the lithography process can print, determines how many transistors ... » read more

Blog Review: Dec. 4
By Jesse Allen - 04 Dec, 2019 - Comments: 0

Arm's Rupal Gandhi digs into the Cell-Aware Test methodology to deterministically target the growing number of defects that occur within the cells, the process of CAT library generation, and compares the static and transition patterns generated. Cadence's Paul McLellan shares highlights from the recent WOSET event with a look at the big drivers for the current interest in open-source EDA too... » read more

Weighing Wafers Simplifies Metrology
By Jiangtao Hu - 21 Nov, 2019 - Comments: 2

Building semiconductors is an incredibly exacting process, with critical dimensions posing significant equipment challenges – and with the possibility that small process excursions can cause the yield to decrease. For this reason, it has always been important to measure and monitor the most critical process steps to ensure that no further processing is done on a faulty lot and so that equipme... » read more

DRAM Scaling Challenges Grow
By Mark LaPedus - 21 Nov, 2019 - Comments: 5

DRAM makers are pushing into the next phase of scaling, but they are facing several challenges as the memory technology approaches its physical limit. DRAM is used for main memory in systems, and today’s most advanced devices are based on roughly 18nm to 15nm processes. The physical limit for DRAM is somewhere around 10nm. There are efforts in R&D to extend the technology, and ultimate... » read more

Building An MRAM Array
By Katherine Derbyshire - 17 Oct, 2019 - Comments: 2

MRAM is gaining traction in a variety of designs as a middle-level type of memory, but there are reasons why it took so long to bring this memory to market. A typical magnetoresistive RAM architecture is based on CoFeB magnetic layers, with an MgO tunneling barrier. The reference layer should have zero net magnetization to make sure that it doesn’t influence the orientation of the free lay... » read more

Node Within A Node
By Ed Sperling - 24 Jul, 2019 - Comments: 0

Enough margin exists in manufacturing processes to carve out the equivalent of a full node of scaling, but shrinking that margin will require a collective push across the entire semiconductor manufacturing supply chain. Margin is built into manufacturing at various stages to ensure that chips are manufacturable and yield sufficiently. It can include everything from variation in how lines are... » read more

Controlling Variability And Cost At 3nm And Beyond
By Ed Sperling - 22 May, 2019 - Comments: 1

Richard Gottscho, executive vice president and CTO of Lam Research, sat down with Semiconductor Engineering to talk about how to utilize more data from sensors in manufacturing equipment, the migration to new process nodes, and advancements in ALE and materials that could have a big impact on controlling costs. What follows are excerpts of that conversation. SE: As more sensors are added int... » read more

ALD Tungsten Solves Capacity Challenges in 3D NAND Device Manufacturing
By Lam Research - 18 Apr, 2019 - Comments: 0

Our increasingly connected and ever “smarter” world generates increasing amounts of data, putting pressure on manufacturers who face new technical challenges in delivering the increasing capacity required for processing and storage. The ALD Tungsten process is helping 3D NAND manufacturers overcome the technical challenges of producing memory chips with higher storage capacity. 3D NAND a... » read more

Manufacturing Bits: March 26
By Mark LaPedus - 26 Mar, 2019 - Comments: 0

ALD materials database Atomic Limits, a blog site that addresses atomic-level processing technologies, has developed an online database listing all atomic layer deposition (ALD) materials and processes. The database could be useful for ALD processes in semiconductors and other fields. ALD is a deposition technique that deposits materials one layer at a time. In ALD systems, wafers are place... » read more

Manufacturing Bits: March 5
By Mark LaPedus - 05 Mar, 2019 - Comments: 0

WAAM process Thales Alenia Space, Cranfield University and Glenalmond Technologies have produced a prototype of a titanium pressure vessel for use in future space missions. The vessel is 1 meter in height and weighs 8.5kg. The titanium alloy is made using Cranfield’s additive technology, dubbed the Wire + Arc Additive Manufacturing (WAAM) process. Related to 3D printing technology, WA... » read more

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