Building An MRAM Array

Why MRAM is so attractive.


MRAM is gaining traction in a variety of designs as a middle-level type of memory, but there are reasons why it took so long to bring this memory to market.

A typical magnetoresistive RAM architecture is based on CoFeB magnetic layers, with an MgO tunneling barrier. The reference layer should have zero net magnetization to make sure that it doesn’t influence the orientation of the free layer. Typical designs accomplish this with two sub-layers, oriented anti-parallel to each other, with an antiferromagnetic material like ruthenium between them. Additional layers also may be needed for lattice matching between the top and bottom electrodes, the magnetic layers, and the tunnel barrier.

Mahendra Pakala, managing director of the Applied Materials Memory Group, explained that the complete structure poses substantial processing challenges. Each of the many component layers requires angstrom-level control of thickness and crystal alignment.

Atomic layer deposition, while commonly used for applications like dielectric oxides, is not suitable here. ALD precursors tend to leave behind oxygen, hydrogen, or both, contaminating the resulting film. ALD films also grow through the nucleation and expansion of individual islands. In contrast, physical vapor deposition (PVD) simply showers a uniform layer of atoms over the wafer. Applied Materials’ Clover PVD chamber can deposit as many as five different materials without breaking vacuum, Pakala said, while integrated heating and cooling stations on the Endura platform facilitate controlled crystallization.

Part of the appeal of MRAM devices is their simplicity, potentially allowing designers to embed them in the back-end-of-line metallization of CMOS logic circuits. At the 2017 Massive Storage Systems and Technology (MSST) conference, TDK’s Luc Thomas explained that such a structure requires only three or four additional mask layers, stacking each memory element immediately above its controlling transistor.

A complete integration scheme requires more than layer deposition, though. In a presentation at IEDM in December, researchers from Tohoku University and Tokyo Electron examined the components of a complete embedded STT-MRAM integration process. The component materials are difficult to etch, they explained, with non-volatile etch products. Pattern transfer typically uses reactive ion etching and is potentially damaging to the magnetic layers. Hydrogen from the etch gas can damage the MgO barrier, while nitrogen forms stable nitrides with both iron and boron.

They identified several process optimizations, including an alternative hydrogen and nitrogen-free etch chemistry, using gas pulsing to remove the etched material in a controlled manner. A low temperature deposition process for the SiN cap layer reduced nitrogen incorporation from that source. These improvements, together with a low-damage MgO deposition process, improved both the thermal stability factor and the switching efficiency of their devices by a factor of 9, while delivering 7-nanosecond write speed at 1.8 volts

As noted above, BEOL annealing can also degrade the MRAM structure. Depending on exactly where the MRAM devices are placed, they might have to endure several hours at temperatures above 400°C. These temperatures can affect the crystallinity of the stack and cause boron migration out of the CoFeB layer into the MgO barrier.

New device, new testing requirements
MRAMs represent largely unexplored territory for integrated circuit testing, using magnetic behavior to control the flow of electrons. As such, they require new testing paradigms, with the same attention to magnetic characteristics as to electrical behavior. Hprobe, a spinoff from the SPINTEC research lab, is in the process of developing a suite of magnetic testing equipment for all steps in the process, from layer deposition to final circuit test.

Generally speaking, manufacturers need to be able to measure the response of each memory element as the magnitude and angle of a magnetic field varies. Such measurements have historically used superconducting magnets. However, according to Hprobe CTO Siamak Salimy, the cooling equipment needed for superconductors introduces vibrational and electrical noise, while the magnets themselves need time to change their orientations. Testing cost is a linear function of testing time, and the company believes the switching speed of its 3D air-cooled magnetic field generator is a significant advantage.

For measuring unpatterned magnetic layers and stacks, the company is developing a tester based on the magneto-optic Kerr effect (MOKE). Related to the Faraday effect, which refers to changes to light transmitted through a magnetic material, the Kerr effect describes changes to light reflected by a magnetic material. The behavior of an incident laser beam reflected from an MRAM stack changes as the applied magnetic field varies. MOKE testing can determine the orientation, coercive field, and thermal stability of the individual layers or the combined stack. As Salimy noted, if the magnetic layers won’t realign themselves in response to a magnetic field, they won’t switch electronically, either.

A second tool, also in development, will initialize the reference layer of the memory array, ensuring that all elements use the same “zero” state. Then, a recently announced parametric tester characterizes the thermal stability and critical current of the devices. These values vary depending on process variability. As a result, TDK’s Luc Thomas explained, the devices in a memory array will have a distribution of critical current values. Each individual device has a switching probability at a given current pulse. For the array as a whole, the write current needs to be large enough to switch the most stubborn memory element, without exceeding the breakdown voltage of the array’s weakest tunneling barrier. The larger the gap between the two values, the more reliable the device is likely to be.

Finally, Hprobe’s functional test step confirms that, under the expected operating conditions, the array behaves as designers intended. For automotive and IoT applications in particular, that includes making sure that environmental magnetic fields and temperature variations do not degrade memory performance.

The potential for control of ferromagnetic switching through electronic spins was first proposed by Nevill Mott in 1936 and was experimentally demonstrated by Albert Fert in 1968. In 1988, the discovery of the giant magnetoresistance effect launched the field of spintronics and its applications in magnetic media.

Still, switchable magnetic memories (MRAMs) proved much more challenging and were almost abandoned before the observation of spin-transfer torque behavior in the early 2000s. In the last few years, STT-MRAM devices appear to have reached a tipping point. Commercial products and dedicated equipment are beginning to appear.

So are STT-MRAMs the “universal memory” that the industry needs? Maybe.

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Andrew Walker says:

Nice article. I like the “maybe” 🙂

Greg Akiki says:

Thank you Katherine for an excellent survey article. The current industry landscape feature many options and it will be interesting to see how these memory options are deployed over the next couple of years, especially the debate between MRAM and ReRam.

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