tag: Apache Design Solutions

ESL Power Optimization Flow Requires Ecosystem
By Ann Mutschler - 14 Apr, 2011 - Comments: 0

The issue of power optimization today is very painful for many chip architects who are tasked with determining, meeting and holding to a tight power envelope. Questions concerning how well and to what extent power can truly be understood at the architectural level, let alone optimized, are the subject of debate. The ITRS’s most recent projection provides some insight as to current market d... » read more

Power Issues In 3D
By Ed Sperling - 14 Apr, 2011 - Comments: 0

By Ann Steffora Mutschler The challenges associated with implementing IP subsystems range from maintaining a consistent I/O voltage, achieving consistency in metal stacks to managing a clock distribution network and creating adequate isolation between subsystems on a chip. It’s enough to make your brain hurt. Add to that 3D or 2.5D stacking and the engineering considerations grow substantial... » read more

Rationalization For Power
By Ed Sperling - 14 Apr, 2011 - Comments: 0

By Ed Sperling Power budgets are becoming almost universally problematic. What used to be a unique headache for the cell-phone market has evolved into an ugly migraine that now includes everything with a battery—and increasingly even those devices that rely on a plug. The result is a cascade of effects that are widespread and growing. And while the drivers of this effort vary widely from ... » read more

Power Budgeting 101
By Aveek Sarkar - 14 Apr, 2011 - Comments: 0

By Aveek Sarkar With all the processing power that is being designed into smart and superphones now, I wonder what would happen if all four multi-GHz processors were to execute simultaneously? How long would that small battery last—and would anyone be able to hold it in their bare hands?   [caption id="attachment_6305" align="alignnone" width="342"] Phone surface temperature as a ... » read more

Advanced Modeling Technologies For Chip, Package, System Co-Analysis And Co-Optimization
By Various Writers - 14 Apr, 2011 - Comments: 0

The traditional approach to chip-package-system (CPS) co-analysis and co-optimization lacks required accuracy and limits productivity. To meet the increasing demands for system cost down calls for a new methodology that is more comprehensive. This white paper outlines the Chip Power Model (CPMT) technologies and solutions available from Apache Design Solutions to help address the CPS convergenc... » read more

The Shocking Side Of 3D
By Ed Sperling - 17 Mar, 2011 - Comments: 0

By Ann Steffora Mutschler The pesky static charge that builds up on your clothing when you forget the dryer sheet is more than just a nuisance when it comes to manufacturing ICs. Add 3D structures and process scaling to the mix and the challenge of adequately protecting those devices grows significantly. While this problem used to be largely an afterthought, the charged-device model type of... » read more

Quicker Turnaround
By Aveek Sarkar - 17 Mar, 2011 - Comments: 0

By Aveek Sarkar Statistics indicate the increase in sales for mobile handsets in the emerging economies will be from the sale of smart phones. According to a Nielsen report, Brazilian sales of smart phones were up 128% in 2010, compared to 2009. These emerging economies have traditionally been served by standard cell phones that provided voice and texting needs (Fig. 1), but the consumers i... » read more

No More Netlist Hacking
By Ed Sperling - 10 Feb, 2011 - Comments: 0

By Ann Steffora Mutschler Prior to availability of advanced physical verification tools, it was not uncommon for engineering teams to hack netlists. It sounds very clandestine, but was done out of the need to get detailed information on particular areas of the chip suspected to be a problem. Performing electrical rules checks (ERC) to improve the correctness and reliability of IC designs b... » read more

The Missing Pieces In Power Modeling—And Who’s Going To Provide Them
By Ed Sperling - 10 Feb, 2011 - Comments: 0

By Ed Sperling The push to develop power models is growing at each node, and at 22nm it will be virtually impossible to proceed without one or more models for power. Providing these kind of models is easier said than done, however. Creating an accurate power model requires accurate data from all the other pieces on a chip that potentially can affect the power. That includes how third-party ... » read more

Chip-Package-System Co-Design
By Matt Elmore - 10 Feb, 2011 - Comments: 0

By Matt Elmore This year’s DesignCon 2011 featured a multitude of advanced topics pertaining to IC design. One topic that came up repeatedly was chip-package-system (CPS) co-design. In each area of application, from mobile to automotive, IC designers have prioritized the need to analyze the chip, package, and PCB as complete system, rather than independent projects. The old days of margins, ... » read more

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