Solid Verification Methodology Essential To Productivity

By Ann Mutschler - 22 Sep, 2011 - Comments: 0

Verifying SoCs from a functional perspective pushes the limits of already lean resources, driving verification teams to seek out new ways to improve productivity of verification tasks. Of course, with the verification task being a time-bound one, the challenge is daunting. It is well understood that consumer electronics is pushing the technology envelope in terms of the amount of technology ... » read more

What A Difference A Decade Makes

By Tiffany Sparks - 22 Sep, 2011 - Comments: 0

By Tiffany Sparks Lately, I find myself in a reflective mood, pondering what’s changed over the past 10 years. Of course, with the 10th anniversary of 9/11 earlier this month, there’s been intense focus on what the world was like 10 years ago and what has changed since that fateful day: the thousands of lives lost, first on 9/11, then the lives lost in Afghanistan and Iraq; the geo-poli... » read more

Testing One, Two, Three

By Ed Sperling - 25 Aug, 2011 - Comments: 0

By Ed Sperling The rule of thumb at 90nm—still one of the mainstream process nodes—has been that test is something you do when a chip is done. You attach electrodes on either side, make sure the signal comes through clearly, and that the SoC functions properly. Try the same thing at 40nm, with multiple power islands, multiple voltage rails, lots of third-party IP and usually a slew of p... » read more

Are Test Engineers More Highly Evolved?

By Kiran Vittal - 25 Aug, 2011 - Comments: 0

In a December 2010 blog, my colleague Ron Craig wrote that 94% of respondents to a survey said that timing constraints were a problem. Well, no surprise there. But 70+% said they planned to simply “try harder” during their next project to avoid these problems. Did they really think that was a viable solution? That blog featured a good illustration of the problem. It gave me a good laugh.... » read more

3D Stacking: A Reality Check

By Ed Sperling - 28 Jul, 2011 - Comments: 0

By Ed Sperling The first 2.5D and 3D chips are expected to arrive next year, with the mainstream chip market expected to follow in 2013. While this trend already has seen its share of hype, stacked die—whether through a series of TSVs in true 3D or through an interposer layer in 2.5D—is as real as Moore’s Law. In fact, it’s a direct result of Moore’s Law. But unlike the progres... » read more

The Evil Doctor

By Atrenta - 28 Jul, 2011 - Comments: 0

I’ve always been a fan of superhero movies. I would say the Terminator series is the last time I really liked Arnold Schwarzenegger. I bet I’m not alone in that opinion. I think it’s terrific when downtrodden bands of X-Men use their strange powers to defeat evil. The summer blockbuster season is in full swing with movies like Green Lantern and Captain America. A good time will be had ... » read more

Understanding Formal Verification Concepts, Part II

By Various Writers - 28 Jul, 2011 - Comments: 0

In this second white paper in a three-part series about formal verification concepts, we examine the assertion-based verification flow and some of the formal verification algorithms. This kind of approach has become necessary as SoC designs become more challenging and as the traditional method of simulation proves too slow, too costly, and insufficient in terms of coverage. To downoload thi... » read more

SoC Design In 5 Years

By Ed Sperling - 30 Jun, 2011 - Comments: 0

By Ed Sperling The semiconductor industry is used to looking at changes every couple of years, based upon the progression of Moore’s Law. But look out further, over the next five years when the most advanced process node is somewhere between 14nm and 16nm, and the job of designing and manufacturing an SoC will look very different. At the center of this change are three very significant tr... » read more

Congestion Mitigation During RTL Development

By Various Writers - 29 Jun, 2011 - Comments: 0

Any survey of chip design teams consistently points to two problem areas impacting quality and schedule of today’s system on chip (SoC) designs. Those areas are: a) completeness of verification, and b) physical design closure for area, timing and power for complex IP’s and SoC’s. With the advent of deep sub-micron technology, these problem areas have become exacerbated. In this White Pape... » read more

Low-Power Solutions At DAC

By Bhanu Kapoor - 16 Jun, 2011 - Comments: 0

By Bhanu Kapoor Power is the main driver of semiconductor process technology related advances recently. One would expect a similar focus in the electronic design automation industry to help designers implement low power designs. However, the latest DAC in San Diego didn’t give the impression that the EDA industry is thinking likewise, perhaps with the exception of verification aspects of low... » read more

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Knowledge Centers
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