tag: Atrenta

Automated Assembly And IP Integration Techniques For SoCs
By Various Writers - 17 Dec, 2009 - Comments: 0

Over the past few years, the consumer revolution has led to a trend in convergence of applications on a single device. The biggest example is the “ Smartphone” – handheld devices such as the iPhone or the BlackBerry that can enable consumers to read e-mail, text friends, create spreadsheets and documents, watch YouTube, play video games, listen to music, take pictures, store them, get d... » read more

Verification Of Multi-Clock Designs: The Bigger Picture
By Various Writers - 19 Nov, 2009 - Comments: 0

Yesterday’s SoCs are today’s blocks and sub-chips. The resultant combination of interfaces, protocols and performance objectives regularly results in many clock domains on a single chip. Often, this is further complicated by multiple modes of operation and the associated range of clocking scenarios. This leads to ever increasing numbers of clock interfaces, where data is transferred betw... » read more

More Choices But Less Design Freedom
By Ed Sperling - 19 Nov, 2009 - Comments: 0

By Ed Sperling “What if” is an indelible part of the lexicon of every SoC architect and design engineer from the front end of the design flow all the way to manufacturing, but while the terminology will persist for years to come the answers and the value of those answers are starting to change. Complexity, cost and the need for better integration have simultaneously increased the numb... » read more

Meeting The Challenge Of Verification In Low-Power Designs
By Ed Sperling - 12 Nov, 2009 - Comments: 0

By Cheryl Ajluni Over the years, new techniques, technologies and design tools have been brought to market with the explicit intent of simplifying design verification. Despite these efforts verification still manages to consume a huge chunk of the time spent during design. By some accounts that number tops 70%. The problem is that verification is hard, and it certainly doesn’t get an easi... » read more

SpyGlass Application In An FPGA To ASIC Conversion Flow
By Various Writers - 29 Oct, 2009 - Comments: 0

Mapping from a field programmable gate array (FPGA) to an application specific IC (ASIC) is subject to some limitations. This white paper identifies some of the most common limitations in this mapping process and shows how the use of Atrenta’s GuideWareTM methodologies and SpyGlass® product family help the designer quickly identify and address these limitations. FPGAs are a perfect platfo... » read more

Considerations For Choosing The Right Low-Power Tools
By Ed Sperling - 15 Oct, 2009 - Comments: 0

By Cheryl Ajluni Regardless of what you are designing these days, one fact holds true: Your design is only as good as the design tools you use. Gone are the days when a design could be done on the back of napkin. Today, engineers require a complex ecosystem of interworking tools to guide them through the complex design flow. This is especially true when it comes to low-power design, as i... » read more

Experts At The Table: What’s Next?
By Ed Sperling - 15 Oct, 2009 - Comments: 0

Low-Power Design sat down with Leon Stok, EDA director for IBM’s System & Technology Group; Antun Domic, senior vice president and general manager of Synopsys’ Implementaton Group; Prasad Subramaniam, vice president of design technology at eSilicon, and Bernard Murphy, chief technology officer at Atrenta. What follows are excerpts of that conversation. By Ed Sperling LPD: Where... » read more

Experts At The Table: What’s Next?
By Ed Sperling - 02 Oct, 2009 - Comments: 0

Low-Power Design sat down with Leon Stok, EDA director for IBM’s System & Technology Group; Antun Domic, senior vice president and general manager of Synopsys’ Implementaton Group; Prasad Subramaniam, vice president of design technology at eSilicon, and Bernard Murphy, chief technology officer at Atrenta. What follows are excerpts of that conversation. LPD: What will happen with ... » read more

Experts At The Table: What’s Next?
By Ed Sperling - 17 Sep, 2009 - Comments: 0

Low-Power Design sat down with Leon Stok, EDA director for IBM’s System & Technology Group; Antun Domic, senior vice president and general manager of Synopsys’ Implementaton Group; Prasad Subramaniam, vice president of design technology at eSilicon, and Bernard Murphy, chief technology officer at Atrenta. What follows are excerpts of that conversation. LPD: What are we facing at ... » read more

Experts At The Table: Building A Better Mousetrap
By Ed Sperling - 28 Aug, 2009 - Comments: 0

Low-Power Design sat down with Richard Zarr, chief technologist for the PowerWise Brand at National Semiconductor; Jon McDonald, technical marketing engineer in Mentor Graphics’ design creation business unit; Prasad Subramaniam, vice president of design technology at eSilicon; Steve Carlson, vice president of marketing at Cadence Design Systems, and David Allen, product director for power at ... » read more

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