tag: BiST

ON Semiconductor Reduces Memory BiST Insertion Time By 6X With Tessent Hierarchical Flow
By Mentor, a Siemens Business - 05 Aug, 2019 - Comments: 0

This paper describes a case study on the insertion of memory BiST for an ON Semiconductor multi-million gate-level netlist with 300 memory instances. The physical implementation will be done using a flat layout. Two different methodologies can be applied when it comes to physical implementation; hierarchical or fullflat. When performing physical implementation as full-flat flow, typically the D... » read more

BiST Grows Up In Automotive
By Ann Mutschler - 12 Jun, 2019 - Comments: 0

Test concepts and methods that have been used for many years in traditional semiconductor and SoC design are now being leveraged for automotive chips, but they need to be adapted and upgraded to enable monitoring of advanced automotive systems during operation of a vehicle. Automotive and safety critical designs have very high quality, reliability, and safety requirements, which pairs pe... » read more

In-Chip Monitoring Becoming Essential Below 10nm
By Ann Mutschler - 20 May, 2019 - Comments: 0

Rising systemic complexity and more potential interactions in heterogeneous designs is making it much more difficult to ensure a chip, or even a block within a chip, will functioning properly without actually monitoring that behavior in real-time. Continuous and sporadic monitoring have been creeping into designs for the past couple of decades. But it hasn’t always been clear how effective... » read more

Meeting ISO 26262 Requirements Using Tessent IC Test Solutions
By Mentor, a Siemens Business - 07 May, 2019 - Comments: 0

As the industry moves towards greater automation in vehicles, suppliers of the ICs used to drive the automotive electronic systems are rapidly adopting solutions to meet ISO 26262 requirements. The Tessent family of IC test products offers the highest defect coverage, in-system non-destructive memory test, hybrid ATPG/Logic BIST, and analog test coverage measurement. These technologies add up t... » read more

Automotive, AI Drive Big Changes In Test
By Ann Mutschler - 25 Apr, 2019 - Comments: 0

Design for test is becoming enormously more challenging at advanced nodes and in increasingly heterogeneous designs, where there may be dozens of different processing elements and memories. Historically, test was considered a necessary but rather mundane task. Much has changed over the past year or so. As systemic complexity rises, and as the role of ICs in safety-critical markets continues ... » read more

Automotive Functional Safety Using LBIST and Other Detection Methods
By Cadence - 24 Apr, 2019 - Comments: 0

Functional safety requirements for safety-critical applications are addressed with the insertion of safety mechanisms to detect and/or correct potential failures: their effectiveness is measured by diagnostic coverage (DC). Built-in-self-test, or BIST, originally developed for manufacturing test, can be used as a detection mechanism for functional safety. However, it requires original values to... » read more

Redefining Expectations for Test
By Synopsys - 24 Apr, 2019 - Comments: 0

New and rapidly expanding applications, such as artificial intelligence and automotive, are increasing in design size and complexity. These evolving market segments require unprecedented levels of quality and long-term reliability, which has created a fundamental shift in both the importance and need for integration of advanced semiconductor test. Synopsys unveiled a new family of test products... » read more

How To Manage DFT For AI Chips
By Rahul Singhal - 09 Apr, 2019 - Comments: 0

Semiconductor companies are racing to develop AI-specific chips to meet the rapidly growing compute requirements for artificial intelligence (AI) systems. AI chips from companies like Graphcore and Mythic are ASICs based on the novel, massively parallel architectures that maximize data processing capabilities for AI workloads. Others, like Intel, Nvidia, and AMD, are optimizing existing archite... » read more

IC Test: Doing It At The Right Place At The Right Time
By Rohit Kapur - 14 Mar, 2019 - Comments: 1

In the real world, we are slaves to our environment. The decisions we make are dependent on the resources available at any given time. In school, I remember coming up with a binary decision diagram (BDD) variable-ordering algorithm that relied on partial BDDs. Was that the best algorithm to determine the variable ordering of a BDD for a design? Probably not. However, it was easy to do as a coll... » read more

Unified Compression and LBIST in a Physically Aware Environment
By Cadence - 27 Feb, 2019 - Comments: 0

Unified compression is a new approach that unifies scan compression and logic built-in self-test (LBIST). It leverages recent innovations from Cadence in physically-aware design for test (DFT) to solve routing congestion and area issues from traditional discrete approaches and delivers a confident path to high-quality test. On a sample design, area savings of 35–47%, and scan wirelength savin... » read more

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