tag: BiST

BIST For Low-Power Devices
By Steve Pateras - 09 May, 2013 - Comments: 0

By Stephen Pateras The persistent growth of mobile computing is driving an increasing need to manage power consumption within semiconductor devices. This has significant implications on the design and test of these devices. Low-power requirements affect test in two separate ways. First, it’s important to ensure that any functional power constraints are met (or at least adequately managed) du... » read more

Welcome To The ‘Probably Good Die’ Era
By Mark LaPedus - 13 Dec, 2012 - Comments: 0

By Mark LaPedus In today’s systems, consumers want more performance and bandwidth with a longer battery life. Some chip segments are keeping up with the demands. Still other areas are falling way behind the curve. Battery life is an obvious problem, but memory bandwidth is under the radar. “Initially, memory bandwidth nearly doubled every two years, but this trend has slowed over the pa... » read more

An Automated Approach To RTL Memory BIST Insertion And Verification
By Various Writers - 09 Aug, 2012 - Comments: 0

ASIC vendors have been traditionally incorporating built-in self test (BIST) and repair solutions in their customers' gate level netlist. This used to be the common industry practice for technology nodes of 65 nm and older. Designers were comfortable writing in-house Perl scripts to replace memory instances with combined memory-BIST (MBIST) instances and make necessary connections. However, for... » read more

Routing Congestion Returns
By Ed Sperling - 26 Jul, 2012 - Comments: 0

By Ed Sperling Routing congestion has returned with a vengeance to SoC design, fueled by the advent of more third-party IP, more memory, a variety of new features, as well as the inability to scale wires at the same rate as transistors. This is certainly not a foreign concept for IC design. The markets for place and route tools were driven largely by the need to automate this kind of operat... » read more

3D Stacked Die Create Unique Test Issues
By Ed Sperling - 02 Dec, 2010 - Comments: 0

By Ann Steffora Mutschler While 3D die stacking promises a number of benefits including smaller footprint, faster speed, lower power and possibly lower cost, testing those devices isn’t going to be simple. There are varying degrees of challenges aligned with varying types of defects that occur throughout the process, from wafer fabrication to package assembly to system-level assembly. And... » read more

Rethinking Test
By Ann Mutschler - 11 Feb, 2010 - Comments: 0

By Ann Steffora Mutschler The responsibility of semiconductor test has long sat solely with the test engineer as the chip designer focused on the functionality of the device. However, particularly in low-power designs, when the device is being tested, much higher power levels are applied than normal functional operation – sometimes causing the device to fail. This ‘false failure’ c... » read more

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