tag: Cadence

Blog Review: June 5
By Jesse Allen - 05 Jun, 2019 - Comments: 0

Mentor's Neil Johnson argues that coverage closure shouldn't have to be mad scramble in the home stretch of development if designers change their early development mindset. In a video, Cadence's Amol Borkar explains Simultaneous Localization and Mapping, or SLAM, from the creation of a map of an unknown environment and understanding the orientation of a camera in this space. Synopsys' Tay... » read more

Week In Review: Design, Low Power
By Jesse Allen - 31 May, 2019 - Comments: 0

M&A NXP will acquire Marvell's Wi-Fi Connectivity business in an all-cash, asset transaction valued at $1.76 billion. The deal includes the Wi-Fi and Bluetooth technology portfolios and related assets; the business employs approximately 550 people worldwide. The deal is expected to close by calendar Q1 2020. Tools Cadence unveiled a data center-optimized FPGA-based prototyping system, ... » read more

How To Integrate An Embedded FPGA
By Brian Bailey - 30 May, 2019 - Comments: 1

Choosing to add programmable logic into an SoC with an eFPGA is just the beginning. Other choices follow involving how many lookup tables (LUTs), how much routing and what topology, how will data be transferred in and out of the fabric, does data need to be coherent with system memory, how will it be programmed and tested, and what RTL functions need to be embedded into the programmable fabric ... » read more

Why IP Quality Is So Difficult To Determine
By Ann Mutschler - 30 May, 2019 - Comments: 0

Differentiating good IP from mediocre or bad IP is getting more difficult, in part because it depends up on how and where it is used and in part because even the best IP may work better in one system than another—even in chips developed by the same vendor. This has been one of the challenges with IP over the years. In many cases, IP is poorly characterized, regardless of whether that IP wa... » read more

SLAM And DSP Implementation
By Cadence - 29 May, 2019 - Comments: 0

With the introduction of simultaneous localization and mapping technology, or SLAM, there comes a need for more sophisticated DSPs to handle the required computations. To address this need, Cadence has introduced the Tensilica Vision Q7 DSP to handle the requirements of SLAM, including high performance, low power, and with an ease of development that engineers can leverage to design new and exc... » read more

Blog Review: May 29
By Jesse Allen - 29 May, 2019 - Comments: 0

Cadence's Meera Collier traces the evolution of computing through the series of bottlenecks the industry has needed to overcome and what's being done to address the latest one. Mentor's Rebecca Lord checks out the use of differential signals to mitigate the effects of electromagnetic interference, noise, and crosstalk in PCBs. Synopsys' Taylor Armerding considers whether Ireland's slow en... » read more

The Changing Landscape of Hardware-Based Verification And Software Development
By Frank Schirrmeister - 24 May, 2019 - Comments: 0

As the EDA is gearing up for its biggest industry event, the Design Automation Conference (DAC), this year in Las Vegas, it is interesting to observe what is going on in hardware-based development of emulation and prototyping. The trends I had outlined after last DAC in 2018—system design, cloud, and machine learning—have only grown stronger and are causing changes in the development landsc... » read more

Week In Review: Design, Low Power
By Jesse Allen - 24 May, 2019 - Comments: 0

M&A Marvell will acquire Avera Semiconductor, the ASIC business of GlobalFoundries, for $650 million in cash at closing plus an additional $90 million in cash if certain business conditions are satisfied within the next 15 months. The agreements include transfer of Avera's revenue base, strategic design wins with infrastructure OEMs, and a new long-term wafer supply agreement between Globa... » read more

Blog Review: May 22
By Jesse Allen - 22 May, 2019 - Comments: 0

Synopsys' Taylor Armerding warns that critical infrastructure is still vulnerable to cyber threats, with Kaspersky finding that 42.7% of the industrial control system computers it protected last year were attacked by malware, email phishing, or other threats. Cadence's Paul McLellan listens in as Jon Masters of Red Hat considers how to tackle speculative execution and branch prediction vulne... » read more

Evolution Of Verification Engineers
By Brian Bailey - 22 May, 2019 - Comments: 0

Semiconductor Engineering sat down to discuss the implications of having an executable specification that drives verification with Hagai Arbel, chief executive officer for VTool; Adnan Hamid, chief executive office for Breker Verification; Mark Olen, product marketing manager for Mentor, a Siemens Business; Jim Hogan, managing partner of Vista Ventures; Sharon Rosenberg, senior solutions archit... » read more

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