tag: Cadence

Week In Review: Auto, Security, Pervasive Computing
By SE Staff - 22 May, 2020 - Comments: 0

Edge, cloud, data center Cadence added new verification IP (VIP) for hyperscalar data centers that supports CXL – Compute Express Link, HBM3, and Ethernet 802.3ck. The VIP are part of Cadence’s Verification Suite. Cadence also released IP for 56G long-reach SerDes on TSMC’s N7 and N6 process technologies. Many Mentor, a Siemens Business, IC design tools are now certified TSMC’s N5 a... » read more

Blog Review: May 20
By Jesse Allen - 20 May, 2020 - Comments: 0

Synopsys' Jonathan Knudsen demystifies fuzzing techniques and why the process of sending targeted, intentionally invalid data is important to determining security. Mentor's Chris Spear explains both the potential benefits and challenges of the UVM Configuration Database and guidelines to improve performance. Cadence's Paul McLellan continues the look back at mobile history with the beginn... » read more

Design For Narrowband IoT
By Ann Mutschler - 20 May, 2020 - Comments: 0

Most low-power chips are designed with the assumption that batteries can be recharged or replaced, but there is a whole set of IoT devices under development that are expected to be always-on, communicate over a cellular infrastructure, and remain functional on a coin-sized lithium-ion battery for a decade or more. Welcome to the world of Narrowband IoT (NB-IoT), a 3GPP standard (also known a... » read more

Choosing Between Static and Dynamic Shapes
By Tyler Lockman - 14 May, 2020 - Comments: 0

That title might be a touch misleading. We’re not here to talk about why to convert shapes between static and dynamic. Rather, I want to talk about why you should NOT be doing this. Every design has some conductor shapes in it (or at least a very large percentage of them). What style to use is a choice that will impact performance through your entire flow; let the shape’s purpose guide you.... » read more

Low-Power Analog
By Brian Bailey - 14 May, 2020 - Comments: 3

Analog circuitry is usually a small part of a large SoC, but it does not scale in the same way as digital circuitry under Moore's Law. The power consumed by analog is becoming an increasing concern, especially for battery-operated devices. At the same time, little automation is available to help analog designers reduce consumption. "Newer consumer devices, like smartphones and wearables, alo... » read more

Auto Power Becoming Much More Complex
By Bryon Moyer - 14 May, 2020 - Comments: 0

Rising electronics content in automobiles is putting increased focus on automotive power delivery networks (PDNs). Safety implications mean that thorough power design and verification, along with novel power isolation techniques, are needed at the vehicle level, involving both electrical and mechanical considerations. The electronic takeover can be measured by the percentage that electronic ... » read more

‘More Than Moore’ Reality Check
By Ann Mutschler - 14 May, 2020 - Comments: 1

The semiconductor industry is embracing multi-die packages as feature scaling hits the limits of physics, but how to get there with the least amount of pain and at the lowest cost is a work in progress. Gaps remain in tooling and methodologies, interconnect standards are still being developed, and there are so many implementations of packaging that the number of choices is often overwhelming. ... » read more

Blog Review: May 13
By Jesse Allen - 13 May, 2020 - Comments: 0

Mentor's Neil Johnson considers when in a project certain verification methods should be deployed and the relative impact of techniques at a given point in subsystem design. Cadence's Paul McLellan looks back at the development of mobile standards with 2G, GSM, and the transition to all-digital transmission. Synopsys' Taylor Armerding highlights five online courses to boost your software ... » read more

Sensing Automotive IC Failures
By Anne Meixner - 12 May, 2020 - Comments: 1

The sooner you detect a failure in any electronic system, the sooner you can act. Together, data analytics and on-chip sensors are poised to boost quality in auto chips and add a growing level of predictive maintenance for vehicles. The ballooning number of chips cars makes it difficult to reach 10 defective parts per billion for every IC that goes into a car.  And requiring that for a 15-y... » read more

Which Chip Interconnect Protocol Is Better?
By Ed Sperling - 11 May, 2020 - Comments: 0

Semiconductor Engineering sat down to the discuss the pros and cons of the Compute Express Link (CXL) and the Cache Coherent Interconnect for Accelerators (CCIX) with Kurt Shuler, vice president of marketing at Arteris IP; Richard Solomon, technical marketing manager for PCI Express controller IP at Synopsys; and Jitendra Mohan, CEO of Astera Labs. What follows are excerpts of that conversation... » read more

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