tag: Cadence

Blog Review: May 8
By Jesse Allen - 08 May, 2019 - Comments: 0

Synopsys' Taylor Armerding warns that the threat of cyber war on the financial system is a real possibility and points to four major vulnerability concerns. Cadence's Meera Collier takes a look at bees and technology, from smart hives to sensors that can be carried on the insects' backs. Mentor's Brent Klingforth argues that electrical and mechanic designers need to seamlessly share infor... » read more

5G Heats Up Base Stations
By Kevin Fogarty - 07 May, 2019 - Comments: 4

Before 5G can be deployed commercially on a large scale, engineers have to solve some stubborn problems—including how to make a hot technology a whole lot cooler. 5G-capable modem chipsets are already on the market from Qualcomm, Samsung, Huawei, MediaTek, Intel and Apple, with some 5G service (LTE-Advanced/LTE-Advanced Pro) available in the U.S. But still mostly missing from the 5G equati... » read more

IP Requires System Context At 6/5/3nm
By Ann Mutschler - 01 May, 2019 - Comments: 0

Driven by each successive generation of semiconductor manufacturing technology, complexity has reached dizzying levels. Every part of the design, verification and manufacturing is more complicated and intense the more transistors are able to be packed onto a die. For these reasons, the entire system must be taken into consideration as a whole – not just as individual building blocks as could ... » read more

Blog Review: May 1
By Jesse Allen - 01 May, 2019 - Comments: 0

Synopsys' Melissa Kirschner questions whether a unified standard for safety-related code development will be enough to secure connected cars as MISRA and AUTOSAR merge C++ guidelines. In a podcast, Mentor's Brent Klingforth and John McMillan share questions and answers about rigid-flex PCB design, including the value of incorporating flexible circuits and the key challenges faced when doing ... » read more

Week In Review: Design, Low Power
By Jesse Allen - 26 Apr, 2019 - Comments: 0

A new working group has been proposed by Accellera to focus on the standardization of analog/mixed signal extensions (AMS) for the Universal Verification Methodology (UVM) standard. “Our ambition is to apply UVM for both digital and analog/mixed-signal verification,” said Martin Barnasconi, Accellera Technical Committee Chair. “The UVM-AMS PWG will assess the benefits of creating analog a... » read more

Automotive, AI Drive Big Changes In Test
By Ann Mutschler - 25 Apr, 2019 - Comments: 0

Design for test is becoming enormously more challenging at advanced nodes and in increasingly heterogeneous designs, where there may be dozens of different processing elements and memories. Historically, test was considered a necessary but rather mundane task. Much has changed over the past year or so. As systemic complexity rises, and as the role of ICs in safety-critical markets continues ... » read more

CDNLive 2019: The Verification Ecosystem Is Growing Stronger And Stronger
By Frank Schirrmeister - 25 Apr, 2019 - Comments: 0

Ecosystems are not only fascinating when it comes to processors like Arm, MIPS, x86, and RISC-V (as I have written before) or for semiconductor technologies like TSMC, GLOBALFOUNDRIES, and Samsung; they are key for success in verification as well. CDNLive Silicon Valley was, again, a great example of the verification ecosystem in action. It showcased the different engines verification tools run... » read more

The Case For Embedded FPGAs Strengthens And Widens
By Brian Bailey - 25 Apr, 2019 - Comments: 2

The embedded FPGA, an IP core integrated into an ASIC or SoC, is winning converts. System architects are starting to see the benefits of eFPGAs, which offer the flexibility of programmable logic without the cost of FPGAs. Programmable logic is especially appealing for accelerating machine learning applications that need frequent updates. An eFPGA can provide some architects the cover they ne... » read more

Automotive Functional Safety Using LBIST and Other Detection Methods
By Cadence - 24 Apr, 2019 - Comments: 0

Functional safety requirements for safety-critical applications are addressed with the insertion of safety mechanisms to detect and/or correct potential failures: their effectiveness is measured by diagnostic coverage (DC). Built-in-self-test, or BIST, originally developed for manufacturing test, can be used as a detection mechanism for functional safety. However, it requires original values to... » read more

Blog Review: April 24
By Jesse Allen - 24 Apr, 2019 - Comments: 0

Rambus' Steven Woo checks out changes in the hardware used for neural network training and the importance of co-design of hardware and software. Cadence's Meera Collier makes an argument for why vehicle sensors watching the driver could prevent some distraction and fatigue-related crashes. Synopsys' Dan Lyon and Garrett Sipple point to some best practices for how to deal with a changing t... » read more

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