tag: Cadence

The Week In Review: Manufacturing
By Mark LaPedus - 12 May, 2017 - Comments: 0

Market research Intel held a slim 4% lead over Samsung for the number one position in terms of chip sales in the first quarter, according to IC Insights. But as reported, Samsung is on pace to displace Intel as the world’s largest semiconductor supplier in the second quarter, according to the firm. Meanwhile, in the ranking, SK Hynix and Micron made the biggest moves. And there was one new e... » read more

The Efficiency Problem
By Samer Hijazi - 11 May, 2017 - Comments: 0

Part one of this report addressed the efficiency problem in neural networks. This segment addresses efficiencies in training, quantization, and optimizing the network and the hardware. Minimize the Bits (CNN Advanced Quantization) Training a CNN involves assigning weight vectors to certain results, and applying adaptive filters to those results to determine the positives, false positives, a... » read more

Power Challenges At 10nm And Below
By Ann Mutschler - 11 May, 2017 - Comments: 1

Current density is becoming much more problematic at 10nm and beyond, increasing the amount of power management that needs to be incorporated into each chip and boosting both design costs and time to market. Current per unit of area has been rising since 90nm, forcing design teams to leverage a number of power-related strategies such as [getkc id="143" kc_name="dynamic voltage and frequency... » read more

Closing The Loop On Power Optimization
By Brian Bailey - 11 May, 2017 - Comments: 2

[getkc id="108" kc_name="Power"] has become a significant limiter for the capabilities of a chip at finer geometries, and making sure that performance is maximized for a given amount of power is becoming a critical design issue. But that is easier said than done, and the tools and methodologies to overcome the limitations of power are still in the early definition stages. The problem spans a... » read more

High-Level Low-Power System Design Optimization
By Cadence - 10 May, 2017 - Comments: 0

High-level decisions have the most impact on power consumption, but the effect of those decisions cannot be known until the hardware is implemented. This paper walks the reader through an industrial high-level low-power design methodology that enables the designer to consider and quantitatively evaluate a broad range of hardware implementations to find the most power-efficient architecture. Thi... » read more

Blog Review: May 10
By Jesse Allen - 10 May, 2017 - Comments: 0

Mentor's Scott Salzwedel checks out what's next for the New Horizons space probe when it comes out of hibernation later this year. Cadence's Paul McLellan provides a look at how NASA took on changing the organization's culture towards safety after the space shuttle Columbia accident. Synopsys' Robert Vamosi points to recent malware that may be affecting between 100K and 200K Windows boxes... » read more

The Week In Review: Design
By Jesse Allen - 05 May, 2017 - Comments: 0

Imagination has put the MIPS embedded processor and Ensigma mobile connectivity groups up for sale, refocusing on graphics after last month's announcement that Apple would no longer use the company's GPU IP. Imagination also began formal dispute resolution procedures with Apple. Tools Synopsys released new versions of its HSPICE, FineSim and CustomSim circuit simulation products, adding n... » read more

Verification And The IoT
By Ed Sperling - 04 May, 2017 - Comments: 0

Semiconductor Engineering sat down to discuss what impact the IoT will have on the design cycle, with Christopher Lawless, director of external customer acceleration in [getentity id="22846" e_name="Intel"]'s Software Services Group; David Lacey, design and verification technologist at Hewlett Packard Enterprise; Jim Hogan, managing partner at Vista Ventures; Frank Schirrmeister, senior group d... » read more

Blog Review: May 3
By Jesse Allen - 03 May, 2017 - Comments: 0

Cadence's Paul McLellan shares highlights from a recent IRDS panel, including changing the assumptions about computing and looking for the next "killer app." Synopsys' Meenakshy Ramachandran introduces the array of improvements in HDMI 2.1, from higher bandwidth to Dynamic HDR. Mentor's Minghui Fan checks out advancements in optical proximity correction and resolution enhancement technolo... » read more

What’s Next In Neural Networking?
By Ann Mutschler - 03 May, 2017 - Comments: 0

Faster chips, more affordable storage, and open libraries are giving neural network new momentum, and companies are now in the process of figuring out how to optimize it across a variety of markets. The roots of neural networking stretch back to the late 1940s with Claude Shannon’s Information Theory, but until several years ago this technology made relatively slow progress. The rush towar... » read more

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