tag: CFETs

The Future Of Transistors And IC Architectures
By Mark LaPedus - 18 Mar, 2021 - Comments: 1

Semiconductor Engineering sat down to discuss chip scaling, transistors, new architectures, and packaging with Jerry Chen, head of global business development for manufacturing & industrials at Nvidia; David Fried, vice president of computational products at Lam Research; Mark Shirey, vice president of marketing and applications at KLA; and Aki Fujimura, CEO of D2S. What follows are excerpt... » read more

Imec’s Plan For Continued Scaling
By Paul McLellan - 14 Jan, 2021 - Comments: 0

At IEDM in December, the opening keynote (technically "Plenary 1") was by Sri Samevadam of Imec. His presentation was titled "Towards Atomic Channels and Deconstructed Chips." He presented Imec's view of the future of semiconductors going forward, both Moore's Law (scaling) and More than Moore (advanced packaging and multiple die). It is always interesting to hear Imec's view of the world sinc... » read more

Speeding Up The R&D Metrology Process
By Mark LaPedus - 16 Jul, 2020 - Comments: 0

Several chipmakers are making some major changes in the characterization/metrology lab, adding more fab-like processes in this group to help speed up chip development times. The characterization/metrology lab, which is generally under the radar, is a group that works with the R&D organization and the fab. The characterization lab is involved in the early analytical work for next-generati... » read more

A Benchmark Study Of Complementary-Field Effect Transistor (CFET) Process Integration Options: Comparing Bulk vs. SOI vs. DSOI Starting Substrates
By Coventor - 17 Jun, 2020 - Comments: 0

Sub-5 nm logic nodes will require an extremely high level of innovation to overcome the inherent real-estate limitations at this increased device density. One approach to increasing device density is to look at the vertical device dimension (z-direction), and stack devices on top of each other instead of conventionally side-by-side. The fabrication of a Complementary-Field Effect Transistor (CF... » read more

A Benchmark Study Of Complementary-Field Effect Transistor (CFET) Process Integration Options Done By Virtual Fabrication
By Coventor - 01 Jun, 2020 - Comments: 0

Four process flow options for Complementary-Field Effect Transistors (C-FET), using different designs and starting substrates (Si bulk, Silicon-On-Insulator, or Double-SOI), were compared to assess the probability of process variation failures. The study was performed using virtual fabrication techniques without requiring fabrication of any actual test wafers. In the study, Nanosheet-on-Nanoshe... » read more

A Node Too Far?
By Ed Sperling - 23 Apr, 2020 - Comments: 1

Physics is an unforgiving master. While the semiconductor industry has been actively developing new transistor structures, new materials for interconnects and lining trenches, and new approaches to alleviate congestion at the lowest metal levels, it also has been playing an accelerating game of Whac-a-Mole. Whenever a problem pops up, the solution to that problem is never complete and more prob... » read more

Making Chips At 3nm And Beyond
By Mark LaPedus and Ed Sperling - 16 Apr, 2020 - Comments: 4

Select foundries are beginning to ramp up their new 5nm processes with 3nm in R&D. The big question is what comes after that. Work is well underway for the 2nm node and beyond, but there are numerous challenges as well as some uncertainty on the horizon. There already are signs that the foundries have pushed out their 3nm production schedules by a few months due to various technical issu... » read more

5/3nm Wars Begin
By Mark LaPedus - 23 Jan, 2020 - Comments: 6

Several foundries are ramping up their new 5nm processes in the market, but now customers must decide whether to design their next chips around the current transistor type or move to a different one at 3nm and beyond. The decision involves the move to extend today’s finFETs to 3nm, or to implement a new technology called gate-all-around FETs (GAA FETs) at 3nm or 2nm. An evolutionary step f... » read more

Variation Issues Grow Wider And Deeper
By Ed Sperling - 24 Jan, 2019 - Comments: 0

Variation is becoming more problematic as chips become increasingly heterogeneous and as they are used in new applications and different locations, sparking concerns about how to solve these issues and what the full impact will be. In the past, variation in semiconductors was considered a foundry issue, typically at the most advanced process node, and largely ignored by most companies. New p... » read more

Where Is Selective Deposition?
By Mark LaPedus - 25 Jun, 2018 - Comments: 4

For years, the industry has been working on an advanced technology called area-selective deposition for chip production at 5nm and beyond. Area-selective deposition, an advanced self-aligned patterning technique, is still in R&D amid a slew of challenges with the technology. But the more advanced forms of technology are beginning to make some progress, possibly inching closer from the la... » read more

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