tag: chiplets

What’s Next In Advanced Packaging
By Mark LaPedus - 20 Jun, 2019 - Comments: 3

Packaging houses are readying the next wave of advanced IC packages, hoping to gain a bigger foothold in the race to develop next-generation chip designs. At a recent event, ASE, Leti/STMicroelectronics, TSMC and others described some of their new and advanced IC packaging technologies, which involve various product categories, such as 2.5D, 3D and fan-out. Some new packaging technologies ar... » read more

Sidestepping Moore’s Law
By Mark LaPedus - 20 Jun, 2019 - Comments: 2

Calvin Cheung, vice president of engineering at ASE, sat down with Semiconductor Engineering to talk about advanced packaging, the challenges involved with the technology, and the implications for Moore’s Law. What follows are excerpts of that conversation. SE: What are some of the big issues with IC packaging today? Cheung: Moore’s Law is slowing down, but transistor scaling will co... » read more

Power, Reliability And Security In Packaging
By Ed Sperling - 19 Jun, 2019 - Comments: 0

Semiconductor Engineering sat down to discuss advanced packaging with Ajay Lalwani, vice president of global manufacturing operations at eSilicon; Vic Kulkarni, vice president and chief strategist in the office of the CTO at ANSYS; Calvin Cheung, vice president of engineering at ASE; Walter Ng, vice president of business management at UMC; and Tien Shiah, senior manager for memory at Samsun... » read more

Playing Into China’s Hands
By Ed Sperling - 13 Jun, 2019 - Comments: 1

The fallout over blacklisting Huawei in particular, and China in general, has set the tone for a nasty global race. But it is almost certain to produce a different result than the proponents of a trade war are expecting. The idea behind tariffs and the blacklisting of Huawei is to starve China of vital technology. So far, the impact has been minimal. Reports from inside of China are equa... » read more

Waiting For Chiplet Interfaces
By Brian Bailey - 13 Jun, 2019 - Comments: 0

There aren't many success stories related to chiplets today for a very simple reason—there are few standard interfaces defined for how to connect them. In fact, the only way to use them is to control both sides of the interface with a proprietary interface and protocol. The one exception is the definition of HBM2, which enables large quantities of third-party DRAM to be connected to a logi... » read more

ECTC Packaging Trends
By Mark LaPedus - 10 Jun, 2019 - Comments: 0

At the recent IEEE Electronic Components and Technology Conference (ECTC) in Las Vegas, a number of packaging houses, R&D organizations and universities presented a slew of papers on the latest IC packaging technologies. The event provided a glimpse of the future of packaging, which is becoming more important in the industry. At one time, IC packaging took a backseat in the semiconductor... » read more

Meltdown, Spectre And Foreshadow
By Ed Sperling - 03 Jun, 2019 - Comments: 0

Ben Levine, senior director of product management for Rambus’ Security Division, talks with Semiconductor Engineering about hardware-specific attacks, why they are so dangerous, and how they work. » read more

Chiplet Momentum Builds, Despite Tradeoffs
By Brian Bailey - 13 May, 2019 - Comments: 0

Chip design is a series of tradeoffs. Some are technical, others are related to cost, competitive features or legal restrictions. But with the nascent 'chiplet' market, many of the established balance points are significantly altered, depending on market segments and ecosystem readiness. Chiplets provide an alternative mechanism for integrating intellectual property (IP) blocks into a semico... » read more

Creating A Roadmap For Hardware Security
By Kevin Fogarty and Ed Sperling - 02 May, 2019 - Comments: 0

The U.S. Department of Defense and private industry consortiums are developing comprehensive and cohesive cybersecurity plans that will serve as blueprints for military, industrial and commercial systems. What is particularly noteworthy in all of these efforts is the focus on semiconductors. While software can be patched, vulnerabilities such as Spectre, Meltdown and Foreshadow need to be de... » read more

Manufacturing Bits: April 23
By Mark LaPedus - 23 Apr, 2019 - Comments: 0

Sorting nuclei CERN and GSI Darmstadt have begun testing the first of two giant magnets that will serve as part of one of the largest and most complex accelerator facilities in the world. CERN, the European Organization for Nuclear Research, recently obtained two magnets from GSI. The two magnets weigh a total of 27 tons. About 60 more magnets will follow over the next five years. These ... » read more

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