Speeding Up Process Optimization With Virtual Processing

By Coventor - 16 Jul, 2020 - Comments: 0

Advanced CMOS scaling and new memory technologies have introduced increasingly complex structures into the device manufacturing process. For example, the increase in NAND memory layers has achieved greater vertical NAND scaling and higher memory density, but has led to challenges in high aspect ratio etch patterning and foot print scaling issues. Unique integration and patterning schemes have b... » read more

Week In Review: Auto, Security, Pervasive Computing

By Susan Rambo - 13 Mar, 2020 - Comments: 0

AI, machine learning Cadence says it has optimized its Tensilica HiFi digital signal processor IP to efficiently execute TensorFlow Lite for Microcontrollers, which are used in Google’s machine learning platform for edge. This means developers of AI/ML on the edge systems can now put better audio processing on edge devices with ML applications like keyword detection, audio scene detection, n... » read more

Going On the Edge

By Mark LaPedus - 27 Jan, 2020 - Comments: 3

Emmanuel Sabonnadière, chief executive of Leti, sat down with Semiconductor Engineering to talk about artificial intelligence (AI), edge computing and chip technologies. What follows are excerpts of that conversation. SE: Where is AI going in the future? Sabonnadière: I am a strong believer that edge AI will change our lives. Today’s microelectronics are organized with 80% of things i... » read more

Speeding Up Process Optimization Using Virtual Fabrication

By Coventor - 22 Jan, 2020 - Comments: 0

Author: Joseph Ervin Director, Semiconductor Process and Integration Lam Research Advanced CMOS scaling and new memory technologies have introduced increasingly complex structures into the device manufacturing process. For example, the increase in NAND memory layers has achieved greater vertical NAND scaling and higher memory density, but has led to challenges in high aspect ratio etch patte... » read more

External Resistance Reduction By Nanosecond Laser Anneal In Si/SiGe CMOS Technology

By Veeco - 18 Sep, 2019 - Comments: 0

Authors: 1Oleg Gluschenkov, 1Heng Wu, 1Kevin Brew, 2Chengyu Niu, 1Lan Yu, 1Yasir Sulehria, 1Samuel Choi, 22Curtis Durfee, 1James Demarest, 1Adra Carr, 3Shaoyin Chen, 3Jim Willis, 3Thirumal Thanigaivelan, 1Fee-li Lie, 2Walter Kleemeier, and 1Dechao Guo 1IBM Research, 257 Fuller Road, Albany, NY 12203, USA, email: [email protected] 2GLOBALFOUNDRIES Inc., Albany, NY, USA, 3ULTRATECH, a division ... » read more

Trading Off Power And Performance Earlier In Designs

By Ann Mutschler - 12 Sep, 2019 - Comments: 0

Optimizing performance, power and reliability in consumer electronics is an engineering feat that involves a series of tradeoffs based on gathering as much data about the use cases in which a design will operate. Approaches vary widely by market, by domain expertise, and by the established methodologies and perspective of the design teams. As a result, one team may opt for a leading-edge des... » read more

Effects of a Random Process Variation on the Transfer Characteristics of a Fundamental Photonic Integrated Circuit Component

By Coventor - 24 Jan, 2019 - Comments: 0

Silicon photonics is rapidly emerging as a promising technology to enable higher bandwidth, lower energy, and lower latency communication and information processing, and other applications. In silicon photonics, existing CMOS manufacturing infrastructure and techniques are leveraged. However, a key challenge for silicon photonics is the lack of mature models that take into account known CMOS pr... » read more

Zeno Semi Expands On-Chip Memory

By Kevin Fogarty - 30 Oct, 2018 - Comments: 0

San Jose, Calif.-based startup Zeno Semiconductor is testing modifications and a smaller process node for the single-transistor 28nm SRAM chip it introduced in 2016, which could boost space for on-chip CPU memory by more than 2.5X, according to the co-founder and CEO of the company, Yuniarto Widjaja. The Zeno-1 transistor is built on standard CMOS processes, has a bi-stable bipolar transisto... » read more

Parametric Analysis, Design Guidelines for mm-Wave nm CMOS Transmission Lines

By Helic - 10 Oct, 2018 - Comments: 0

This paper focuses on nm CMOS transmission line design as distributed passive elements and their application in mm-wave integrated circuits. A variety of transmission lines such as coplanar waveguides (CPWs), shielded coplanar waveguides (SCPWs), and CPW with ground are analyzed in terms of their geometry and electrical properties. The parametric analysis of the various line types is based on a... » read more

AI Architectures Must Change

By Brian Bailey - 13 Aug, 2018 - Comments: 4

Using existing architectures for solving machine learning and artificial intelligence problems is becoming impractical. The total energy consumed by AI is rising significantly, and CPUs and GPUs increasingly are looking like the wrong tools for the job. Several roundtables have concluded the best opportunity for significant change happens when there is no legacy IP. Most designs have evolved... » read more

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tag: CMOS