tag: CMOS

40 GHz VCO and Frequency Divider in 28 nm FD-SOI CMOS Technology for Automotive Radar Sensors
By Technical Paper Link - 31 Aug, 2021 - Comments: 0

Abstract: "This paper presents a 40 GHz voltage-controlled oscillator (VCO) and frequency divider chain fabricated in STMicroelectronics 28 nm ultrathin body and box (UTBB) fully depleted silicon-on-insulator (FD-SOI) complementary metal-oxide–semiconductor (CMOS) process with eight metal layers back-end-of-line (BEOL) option. VCOs architecture is based on an LC-tank with p-type metal-oxide�... » read more

Plasma processing for advanced microelectronics beyond CMOS
By Technical Paper Link - 27 Aug, 2021 - Comments: 0

N. Marchack, L. Buzi, D. B. Farmer, H. Miyazoe, J. M. Papalia, H. Yan, G. Totir, and S. U. Engelmann , "Plasma processing for advanced microelectronics beyond CMOS", Journal of Applied Physics 130, 080901 (2021) https://doi.org/10.1063/5.0053666 ABSTRACT "The scientific study of plasma discharges and their material interactions has been crucial to the development of semiconductor process en... » read more

Bonding Issues For Multi-Chip Packages
By Katherine Derbyshire - 19 Nov, 2020 - Comments: 1

The rising cost and complexity of developing chips at the most advanced nodes is forcing many chipmakers to begin breaking up that chip into multiple parts, not all of which require leading edge nodes. The challenge is how to put those disaggregated pieces back together. When a complex system is integrated monolithically — on a single piece of silicon — the final product is a compromise ... » read more

Graphene and two-dimensional materials for silicon technology
By Technical Paper Link - 02 Oct, 2020 - Comments: 1

Abstract: "The development of silicon semiconductor technology has produced breakthroughs in electronics—from the microprocessor in the late 1960s to early 1970s, to automation, computers and smartphones—by downscaling the physical size of devices and wires to the nanometre regime. Now, graphene and related two-dimensional (2D) materials offer prospects of unprecedented advances in device ... » read more

Speeding Up Process Optimization With Virtual Processing
By Coventor - 16 Jul, 2020 - Comments: 0

Advanced CMOS scaling and new memory technologies have introduced increasingly complex structures into the device manufacturing process. For example, the increase in NAND memory layers has achieved greater vertical NAND scaling and higher memory density, but has led to challenges in high aspect ratio etch patterning and foot print scaling issues. Unique integration and patterning schemes have b... » read more

Week In Review: Auto, Security, Pervasive Computing
By Susan Rambo - 13 Mar, 2020 - Comments: 0

AI, machine learning Cadence says it has optimized its Tensilica HiFi digital signal processor IP to efficiently execute TensorFlow Lite for Microcontrollers, which are used in Google’s machine learning platform for edge. This means developers of AI/ML on the edge systems can now put better audio processing on edge devices with ML applications like keyword detection, audio scene detection, n... » read more

Going On the Edge
By Mark LaPedus - 27 Jan, 2020 - Comments: 3

Emmanuel Sabonnadière, chief executive of Leti, sat down with Semiconductor Engineering to talk about artificial intelligence (AI), edge computing and chip technologies. What follows are excerpts of that conversation. SE: Where is AI going in the future? Sabonnadière: I am a strong believer that edge AI will change our lives. Today’s microelectronics are organized with 80% of things i... » read more

Speeding Up Process Optimization Using Virtual Fabrication
By Coventor - 22 Jan, 2020 - Comments: 0

Author: Joseph Ervin Director, Semiconductor Process and Integration Lam Research Advanced CMOS scaling and new memory technologies have introduced increasingly complex structures into the device manufacturing process. For example, the increase in NAND memory layers has achieved greater vertical NAND scaling and higher memory density, but has led to challenges in high aspect ratio etch patte... » read more

External Resistance Reduction By Nanosecond Laser Anneal In Si/SiGe CMOS Technology
By Veeco - 18 Sep, 2019 - Comments: 0

Authors: 1Oleg Gluschenkov, 1Heng Wu, 1Kevin Brew, 2Chengyu Niu, 1Lan Yu, 1Yasir Sulehria, 1Samuel Choi, 22Curtis Durfee, 1James Demarest, 1Adra Carr, 3Shaoyin Chen, 3Jim Willis, 3Thirumal Thanigaivelan, 1Fee-li Lie, 2Walter Kleemeier, and 1Dechao Guo 1IBM Research, 257 Fuller Road, Albany, NY 12203, USA, email: [email protected] 2GLOBALFOUNDRIES Inc., Albany, NY, USA, 3ULTRATECH, a division ... » read more

Trading Off Power And Performance Earlier In Designs
By Ann Mutschler - 12 Sep, 2019 - Comments: 0

Optimizing performance, power and reliability in consumer electronics is an engineering feat that involves a series of tradeoffs based on gathering as much data about the use cases in which a design will operate. Approaches vary widely by market, by domain expertise, and by the established methodologies and perspective of the design teams. As a result, one team may opt for a leading-edge des... » read more

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