tag: Coventor

Identifying DRAM Failures Caused By Leakage Current And Parasitic Capacitance
By Taeyon (TY) Oh - 03 Feb, 2020 - Comments: 0

Leakage current has been a leading cause of device failure in DRAM design, starting with the 20nm technology node. Problems with leakage current in DRAM design can lead to reliability issues, even when there are no obvious structural abnormalities in the underlying device. Leakage current has become a critically important component in DRAM device design. Fig. 1 (a) DRAM Memory Cell, (b) GI... » read more

Speeding Up Process Optimization Using Virtual Fabrication
By Coventor - 22 Jan, 2020 - Comments: 0

Author: Joseph Ervin Director, Semiconductor Process and Integration Lam Research Advanced CMOS scaling and new memory technologies have introduced increasingly complex structures into the device manufacturing process. For example, the increase in NAND memory layers has achieved greater vertical NAND scaling and higher memory density, but has led to challenges in high aspect ratio etch patte... » read more

Week In Review: Manufacturing, Test
By Mark LaPedus - 10 Jan, 2020 - Comments: 1

Chipmakers A fire broke out this week at a joint NAND flash fab between Western Digital (WD) and Kioxia. Kioxia is the former Toshiba NAND flash unit that was recently spun out by the Japanese company. “On Monday, January 6, (morning, January 7 local time) a small fire occurred at one of our joint venture facilities in Yokkaichi, Japan. Local firefighters quickly extinguished the fire, and w... » read more

An Introduction To Semiconductor Process Modeling
By Jeonghoon (James) Kim - 20 Dec, 2019 - Comments: 0

Semiconductor process engineers would love to develop successful process recipes without the guesswork of repeated wafer testing. Unfortunately, developing a successful process can’t be done without some work. This blog will discuss an efficient technique to develop new process steps faster, with much less effort. Basic concept The easiest way to predict a process result is to model its b... » read more

N7 FinFET Self-Aligned Quadruple Patterning Modeling
By Coventor - 16 Dec, 2019 - Comments: 0

In this paper, we model fin pitch walk based on a process flow simulation using the Coventor SEMulator3D virtual platform. A taper angle of the fin core is introduced into the model to provide good agreement with silicon data. The impact on various Self-Aligned Quadruple Patterning process steps is assessed. Etch sensitivity to pattern density is reproduced in the model and provides insight on ... » read more

A Study Of Next-Generation CFET Process Integration Options
By Benjamin Vincent - 21 Nov, 2019 - Comments: 0

Decision making is a critical step in semiconductor technology development. R&D semiconductor engineers must consider different design and process options early in the development of a next-generation technology. Established techniques such as Failure Mode and Effect Analysis (FMEA) can be used to select among the most promising design and process choices. Once specific design and process m... » read more

A Benchmark Study Of Complementary-Field Effect Transistor (CFET) Process Integration Options
By Coventor - 21 Nov, 2019 - Comments: 0

Sub-5 nm logic nodes will require an extremely high level of innovation to overcome the inherent real-estate limitations at this increased device density. One approach to increasing device density is to look at the vertical device dimension (z-direction), and stack devices on top of each other instead of conventionally side-by-side. [1] The fabrication of a Complementary-Field Effect Transistor... » read more

Making Random Variation Less Random
By Ed Sperling - 21 Oct, 2019 - Comments: 0

The economics for random variation are changing, particularly at advanced nodes and in complex packaging schemes. Random variation always will exist in semiconductor manufacturing processes, but much of what is called random has a traceable root cause. The reason it is classified as random is that it is expensive to track down all of the various quirks in a complex manufacturing process or i... » read more

Week In Review: Manufacturing, Test
By Mark LaPedus - 18 Oct, 2019 - Comments: 0

Chipmakers The semiconductor capital spending race continues to escalate in the leading-edge logic space. Intel and Samsung have separately announced big capital spending plans in 2019. Intel’s latest CapEx budget is $15.5 billion in 2019, while Samsung’s CapEx is slated for $16.204 billion for the year, according to KeyBanc Capital Markets. Now, TSMC is raising the stakes. TSMC this... » read more

Advances In 3D CMOS Image Sensors Optical Modeling: Combining Realistic Morphologies With FDTD
By Coventor - 16 Oct, 2019 - Comments: 0

This paper describes an innovative methodology to investigate the relationship between device morphology and the optical performance of CMOS image sensors. By coupling a FDTD-based 3D Maxwell solver with silicon-accurate process modeling software, we have been able to analyze the sensitivity of image sensor quantum efficiency with respect to statistical variations in nm-scale device topology. A... » read more

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