tag: Coventor

The Week In Review: Manufacturing
By Mark LaPedus - 11 May, 2018 - Comments: 0

Test and packaging In a major surprise, Cohu has entered into a definitive agreement to acquire Xcerra for approximately $796 million. With the deal, Cohu will enter the ATE market. Last year, a group from China entered into a definitive agreement under which it would acquire Xcerra. But the U.S. blocked Xcerra’s sale to the Chinese group. Ironically, at one time, Cohu was reportedly lobbyin... » read more

Advanced 3D Design Technology Co-Optimization For Manufacturability
By Yu De Chen - 30 Apr, 2018 - Comments: 0

By Yu De Chen, Jacky Huang, Dalong Zhao, Jiangjiang (Jimmy) Gu, and Joseph Ervin Yield and cost have always been critical factors for both manufacturers and designers of semiconductor products. It is a continuous challenge to meet targets of both yield and cost, due to new device structures and the increasing complexity of process innovations introduced to achieve improved product performanc... » read more

Blog Review: Apr. 25
By Jesse Allen - 25 Apr, 2018 - Comments: 0

Mentor's Cristian Filip digs into SerDes design with a focus on the adoption and evolution of Channel Operating Margin (COM) as a tool for ensuring compliance of high-speed designs and why it's useful even if its mathematical procedure might be intimidating at the beginning. Cadence's Paul McLellan explains the importance of IBIS and AMI standards for SerDes design and why the upcoming DDR5 ... » read more

Design Rule Complexity Rising
By Ed Sperling - 19 Apr, 2018 - Comments: 0

Variation, edge placement error, and a variety of other issues at new process geometries are forcing chipmakers and EDA vendors to confront a growing volume of increasingly complex, and sometimes interconnected design rules to ensure chips are manufacturable. The number of rules has increased to the point where it's impossible to manually keep track of all of them, and that has led to new pr... » read more

Modeling Semiconductor Process Variation
By Coventor - 19 Apr, 2018 - Comments: 0

3D semiconductors, 3D NAND Flash, FinFETS and other advanced devices are bringing tremendous opportunities to the semiconductor industry. Unfortunately, these devices are also bringing new design, process and production problems. Process variability has been a major contributor to production delays as feature sizes have decreased and process complexity has increased. Virtual fabrication is a co... » read more

What Happened To Nanoimprint Litho?
By Mark LaPedus - 29 Mar, 2018 - Comments: 4

Nanoimprint lithography (NIL) is re-emerging amid an explosion of new applications in the market. Canon, EV Group, Nanonex, Suss and others continue to develop and ship NIL systems for a range of markets. NIL is different than conventional lithography and resembles a stamping process. Initially, a lithographic system forms a pattern on a template based on a pre-defined design. Then, a separa... » read more

Self-Aligned Block And Fully Self-Aligned Via For iN5 Metal 2 Self-Aligned Quadruple Patterning
By Coventor - 29 Mar, 2018 - Comments: 0

This paper assesses Self-Aligned Block (SAB) and Fully Self-Aligned Via (FSAV) approaches to patterning using a iN5 (imec node 5 nm) vehicle and Metal 2 Self-Aligned Quadruple Patterning. We analyze SAB printability in the lithography process using process optimization, and demonstrate the effect of SAB on patterning yield for a (8 M2 lines x 6 M1 lines x 6 Via) structure. We show that FSAV, co... » read more

Improving Patterning Yield At The 5nm Semiconductor Node
By Benjamin Vincent - 29 Mar, 2018 - Comments: 0

Engineering decisions are always data-driven. As scientists, we only believe in facts and not in intuition or feelings. At the manufacturing stage, the semiconductor industry is eager to provide data and facts to engineers based upon metrics such as the quantity of wafers produced per hour and sites/devices tested on each of those wafers. The massive quantity of data generated in semiconduct... » read more

DSA Re-Enters Litho Picture
By Mark LaPedus - 15 Mar, 2018 - Comments: 1

By Mark LaPedus and Ed Sperling Directed self-assembly (DSA) is moving back onto the patterning radar screen amid ongoing challenges in lithography. Intel continues to have a keen interest in [gettech id="31046" t_name="DSA"], while other chipmakers are taking another hard look at the technology, according to multiple industry sources. DSA isn't like a traditional [getkc id="80" kc_name="... » read more

The Next 5 Years Of Chip Technology
By Ed Sperling - 14 Mar, 2018 - Comments: 0

Semiconductor Engineering sat down to discuss the future of scaling, the impact of variation, and the introduction of new materials and technologies, with Rick Gottscho, CTO of Lam Research; Mark Dougherty, vice president of advanced module engineering at GlobalFoundries; David Shortt, technical fellow at KLA-Tencor; Gary Zhang, vice president of computational litho products at ASML; and Shay... » read more

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