tag: Coventor

The Impact Of Metal Gate Recess Profile On Transistor Resistance And Capacitance
By Pradeep Nanja - 18 May, 2023 - Comments: 0

In logic devices such as finFETs (field-effect transistors), metal gate parasitic capacitance can negatively impact electrical performance. One way to reduce this parasitic capacitance is to optimize the metal gate recess dimensions. However, there are limits to reducing this capacitance if you simply remove more of the metal material, since this can modify capacitance unexpectedly through chan... » read more

A Deposition And Etch Technique To Lower Resistance Of Semiconductor Metal Lines
By Timothy Yang - 20 Apr, 2023 - Comments: 0

Copper's resistivity depends on its crystal structure, void volume, grain boundaries and material interface mismatch, which becomes more significant at smaller scales. The formation of copper (Cu) wires is traditionally done by etching a trench pattern in low-k silicon dioxide using a trench etch process, and subsequently filling the trench with Cu via a damascene flow. Unfortunately, this meth... » read more

Blog Review: April 19
By Jesse Allen - 19 Apr, 2023 - Comments: 0

Synopsys' Soren Smidstrup and Kerim Genc explore how materials modeling helps battery designers explore the wide playing field for new battery materials and optimize performance by co-designing the structure and chemistry of new batteries, ultimately shortening development time and cost. Siemens' Stephen Chavez finds that enabling multiple engineers to work simultaneously within the same PCB... » read more

Blog Review: March 29
By Jesse Allen - 29 Mar, 2023 - Comments: 0

Siemens' Heather George suggests adopting a shift-left strategy for complex designs that integrate multiple dies into a package and examines the challenges and opportunities for performing comprehensive tests on 2.5D and 3D IC designs. Synopsys' Shekhar Kapoor notes that when considering whether a system will perform as intended, techniques that work well for monolithic SoCs may not be as we... » read more

A Comparative Evaluation Of DRAM Bit-Line Spacer Integration Schemes
By Dempsey Deng - 16 Mar, 2023 - Comments: 0

With decreasing dynamic random-access memory (DRAM) cell sizes, DRAM process development has become increasingly difficult. Bit-line (BL) sensing margins and refresh times have become problematic as cell sizes have decreased, due to an increase in BL parasitic capacitance (Cb). The main factor impacting Cb is the parasitic capacitance between the BL and the node contact (CBL-NC) [1]. To reduce ... » read more

Blog Review: March 1
By Jesse Allen - 01 Mar, 2023 - Comments: 0

Siemens EDA's Chris Spear explains the UVM Factory and how it can facilitate collaboration by enabling injection of new features without affecting your team. Cadence's Paul McLellan looks at efforts to ensure chiplets from different companies work together, particularly when the creating companies didn't pre-plan for those specific chiplets to work together, as well as the problems of failur... » read more

The Other Side Of The Wafer: The Latest Developments In Backside Power Delivery
By Sandy Wen - 16 Feb, 2023 - Comments: 0

At the beginning of my career in semiconductor equipment, the backside of the wafer was a source of anxiety. In one memorable instance in my early career, several wafers flew off a robot blade during a wafer transfer. After cleaning up the mess, we remembered that a variety of thin films could be deposited on the wafer backside, which could decrease its friction coefficient. Slowing down the wa... » read more

Blog Review: Feb. 8
By Jesse Allen - 08 Feb, 2023 - Comments: 0

Cadence's Sanjeet Kumar points to key changes and optimizations that are done for USB3 Gen T compared to USB3 Gen X tunneling in order to minimize tunnel overhead and maximize USB3 throughput. Siemens EDA's Harry Foster considers the effectiveness of IC and ASIC verification by looking at schedule overruns, number of required spins, and classification of functional bugs. Synopsys' Chris C... » read more

Big Changes Ahead For Chip Technology And Industry Dynamics
By Ed Sperling - 08 Feb, 2023 - Comments: 0

Semiconductor Engineering sat down to discuss the impact of customization and advanced packaging, and concerns about reliability and geopolitical rivalries with Martin van den Brink, president and CTO of ASML; Luc Van den Hove, CEO of imec; David Fried, vice president of computational products at Lam Research; and Ankur Gupta, vice president and general manager of the test group and lifecycle s... » read more

Collaboration Widens Among Big Chip Companies
By Ed Sperling - 23 Jan, 2023 - Comments: 1

Experts at the Table: Semiconductor Engineering sat down to discuss the growing need for collaboration among equipment and tools vendors, the impact of systems companies and increases in complexity, and how to handle a push for more customization while controlling costs, with Martin van den Brink, president and CTO of ASML; Luc Van den Hove, CEO of imec; David Fried, vice president of computati... » read more

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