tag: DFT

Lab-To-Fab Testing
By Ed Sperling - 08 Oct, 2018 - Comments: 0

Test equipment vendors are working on integrating testing and simulation in the lab with testing done later in the fab, setting the stage for what potentially could be the most significant change in semiconductor test in years. If they are successful, this could greatly simplify design for test, which has become increasingly difficult as chips get more complex, denser, and as more heterogene... » read more

The Race To Zero Defects
By Jeff Dorsch - 10 Sep, 2018 - Comments: 1

By Jeff Dorsch and Ed Sperling Testing chips is becoming more difficult, more time-consuming, and much more critical—particularly as these chips end up in cars, industrial automation, and a variety of edge devices. Now the question is how to provide enough test coverage to ensure that chips will work as expected without slowing down the manufacturing process or driving up costs. Balanci... » read more

Digital IC Bring-Up With A Bench-Top Environment
By Matthew Knowles - 23 Aug, 2018 - Comments: 0

One of the hottest markets for IC today is artificial intelligence (AI). The designs for AI chips are also among the largest and most complex, with billions of transistors, thousands of memory instances, and complex design-for-test (DFT) implementations with unique bring up and debug requirements. At this point, the volume of new AI chips is relatively low, but time-to-market is of paramount im... » read more

Accelerating Test Pattern Bring-Up For Rapid First Silicon Debug
By Mentor, a Siemens Business - 22 Aug, 2018 - Comments: 0

Reducing the time spent on silicon bring-up is critical in getting ICs into the hands of customers and staying competitive. Typically, the silicon bring-up process involves converting the test patterns to a tester-specific format and generating a test program that is executed by Automatic Test Equipment (ATE). This standard silicon bring-up flow is becoming too slow and expensive, especially fo... » read more

Changing The Design Flow
By Ed Sperling - 07 Aug, 2018 - Comments: 0

Synopsys’ Michael Jackson talks with Semiconductor Engineering about why it’s becoming necessary to fuse together various pieces of digital design. https://youtu.be/AOWh4wjw-ps » read more

Accelerating Test Pattern Bring-Up For Rapid First Silicon Debug
By Mentor, a Siemens Business - 12 Jul, 2018 - Comments: 0

Reducing the time spent on silicon bring-up is critical in getting ICs into the hands of customers and staying competitive. Typically, the silicon bring-up process involves converting the test patterns to a tester-specific format and generating a test program that is executed by Automatic Test Equipment (ATE). This standard silicon bring-up flow is becoming too slow and expensive, especially fo... » read more

Putting “Design” Back Into Design For Test In PCB Products
By Mentor, a Siemens Business - 11 Jun, 2018 - Comments: 0

Design for manufacturing (DFM) has become a proactive part of the design process, but the same cannot be said for DFT. Whereas “left-shifting” DFM has reduced manufacturing problems, increased yield, reduced scrap levels, and simplified engineering rework, testability-related improvements have stayed flat during that same time. Unfortunately, as assembly costs have come down, and test-relat... » read more

Looking At Test Differently
By Ed Sperling - 05 Mar, 2018 - Comments: 1

Wilhelm Radermacher, executive advisor at [getentity id="22816" e_name="Advantest"], sat down with Semiconductor Engineering to discuss how the impact of rapid market changes, advanced packaging approaches and increasing complexity on test strategies and equipment. What follows are excerpts of that conversation. SE: As we move into new markets where use models and stresses on devices are dif... » read more

A Simple Way To Improve Automotive In-System Test
By Jeff Mayer - 11 Jan, 2018 - Comments: 0

The remarkable growth in automotive IC design has prompted a focus on ISO26262 functional safety compliance, which includes both high-quality manufacturing test and a minimum stuck-at test coverage of 90% for in-system test. Designers must also control IC test data volumes, test application times, and test costs. A new test point technology that improves in-system test coverage and reduces patt... » read more

Tessent MissionMode: New Inline DFT Technology
By Mentor Graphics Staff Writers - 08 Jan, 2018 - Comments: 0

Written for automotive OEMs and suppliers, this whitepaper gives an overview of design-for-test (DFT) technology. Among the topics addressed: Why is DFT important in IC design generally and critical for creating automotive ICs in particular? And how does the new Tessent MissionMode technology, teamed with some of Mentor’s other DFT offerings, pave the way for the automotive industry to develo... » read more

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