The Precision Knob

Precision used to be a goal, but increasingly it is being used as a tool.

This is true for processing and algorithms, where less precision can greatly improve both performance and battery life. And it is true in manufacturing, where more precision can help minimize the growing impact of variation. Moreover, being able to dial precision up or down can help engineers see the impact on a system, as well as imperfections in the individual circuits that may or may not cause fatal defects.

The challenge with precision is knowing what is needed for any particular task or step in a process, when more or less precision is needed, and having enough control to make important tradeoffs. And this leads to a couple of different challenges.

First, semiconductor manufacturing equipment needs to be able to detect variations. For gases and liquids used to develop chips and wafers, as well as man-made materials and compounds used inside those chips or for growing structures on those chips, there needs to be enough resolution in the inspection, metrology and testing to identify irregularities. This can be done in real-time using inspection and a variety of customized sensors, or it can be done post-manufacturing using data analytics. But either way, identifying variation of any sort is essential as chips move from 7nm to 5nm, and it will become even more critical as designs move down to 3nm because those variations will affect yield.

Variation comes in multiple flavors, and many types of variation are additive. This is nothing new. Variation has been present in chip manufacturing since its inception. What has changed are the tolerances for that variation, which are getting tighter at each new node. A defect at 28nm might have caused no issues for the lifetime of a product, while a defect at 7nm could kill a chip—or worse, compromise an expensive multi-chip package. Consider AI systems in autonomous vehicles, for example, where excessive vibration and extreme temperature swings can exacerbate any weakness in a chip or module.

How this affects the overall cost isn’t entirely clear, because much of this needs to be looked at from a total manufacturing cost. Spotting problems at 5nm will require a whole new generation of equipment—or at least significant upgrades to existing equipment—that can identify problems early enough to speed up time-to-yield. That almost certainly will increase manufacturing costs up front. The question for chip manufacturers and packaging houses is whether faster time to yield, and potentially higher yield, will make up the difference.

Second, design tools and flows—design for manufacturing, design for test, design for yield—need to become much more aligned with manufacturing processes at each new node. The collaboration between EDA companies and foundries and packaging houses has been increasing steadily for some time, but the next couple nodes will require much tighter partnerships than in the past. Data needs to flow in two directions rather than just from the foundry to the EDA and IP companies, particularly about what gets designed versus what gets printed on a wafer.

The goal here is to increase precision on both sides wherever it is needed (and to be able to back out of that precision when required) so that margin can be reduced in a design and waste can be eliminated on the manufacturing side. At 5nm, extra circuitry will have a big impact on both heat, which will affect the reliability of chips, and on overall performance and power requirements. Foundries need to understand where the challenges are on the design side, and packaging houses need tools to automate the interactions and possible violations of rules so that different packaging options are more predictable, less expensive, and much less difficult to implement.

Precision is an important element in all of this, and it is becoming much more critical and useful as the supply chain begins to understand when, where and how it can be applied.

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